VHDL to Verilog Problem !

[angjohn]

do u any1 of u know how to translate foolwing VHDL code to Verilog other than the verilog source code i show below ( can any1 know how to translate the code to verilog without using the disable Stament)!

VHDL :

-- BitComparator
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity BitComparator is
	port (
		d : in STD_LOGIC_VECTOR(15 downto 0);
		whichbit : in STD_LOGIC_VECTOR(3 downto 0);
		set : out STD_LOGIC;
		en : in STD_LOGIC;
		CLK : in STD_LOGIC
	);
end BitComparator;

architecture BitComparator_arch of BitComparator is
	signal BitSelect : STD_LOGIC;
begin
	-- Enter concurrent statements here
	
	process(clk, en) 
	begin
		if(clk'event and clk='1') then
			
			--BitSelect <= '0';
			
			if (en = '1') then
				for i in 0 to 15 loop
					BitSelect <= d(i);
					exit when (i = whichbit); 
				end loop;
			end if;
		end if;
	end Process;
	
	Set <= BitSelect;
	
	
end BitComparator_arch;

Verilog

// BitComparator
module BitComparator (d, whichbit, set, en, CLK);

   input[15:0] d; 
   input[3:0] whichbit; 
   output set; 
   wire set;
   input en; 
   input CLK; 

   reg BitSelect; 

   always @(posedge CLK)
   begin
         if (en == 1'b1)
         begin
            begin : compare
               integer i;
               for(i = 0; i <= 15; i = i + 1)
               begin
                  BitSelect <= d[i] ; 
                  if ((i == whichbit)) disable compare; 
               end
            end 
         end 
   end 
   assign set = BitSelect ;
endmodule

 

[tongson]

u can use the software to translate it.

 

[chaitu2k]

can anyone foward or suggest good verilog to vhdl conversion and vice versa software....

also are there any drawbacks in using the conversion softwares

 

[nand_gates]

Here is the translated code!
The best tool is ur BRAIN!!!

// BitComparator
module BitComparator (d, whichbit, set, en, CLK);
   input[15:0] d;
   input[3:0] whichbit;
   output set;
   
   input en;
   input CLK;

   reg         set;
   always @(posedge CLK)
         if (en == 1'b1) 
             set <= d[whichbit] ;
endmodule

 

[adap]

You can write the Verilog code without using the disable statement as follows:

 if (en == 1'b1)
         begin
            begin : compare
               integer i;
               for(i = 0; i <= 15; i = i + 1)
               begin
                   if (i < whichbit)
                     BitSelect <= d[i] ;
               end
            end
         end

 

[maxer]

use x-hdl software


maxer