VHDL testbench fo my design

[91divine]

Hello... i have made a vhdl code for butterworth low pass filter. Please help me in writing a test bench code with different frequency sine wave as input...as i dont know how to generate sine wave in vhdl

My code is, any improvement in code is also invited

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity lpf is
port( Clk : in std_logic;
Xin : in signed(7 downto 0);
Yout : out signed(15 downto 0)
);
end lpf;

architecture Behavioral of lpf is

component DFF is
port(
Q : out signed(15 downto 0);
Clk :in std_logic;
D :in signed(15 downto 0)
);
end component;

signal H0,H1,H2,H3,H4,H5 : signed(7 downto 0) := (others => '0');
signal MCM0,MCM1,MCM2,MCM3,MCM4,MCM5,add_out1,add_out2,ad d_out3,add_out4,add_out5 : signed(15 downto 0) := (others => '0');
signal Q1,Q2,Q3,Q4,Q5 : signed(15 downto 0) := (others => '0');

begin
--filter cofficients

H0 <= to_signed(1,8);
H1 <= to_signed(2,8);
H2 <= to_signed(4,8);
H3 <= to_signed(5,8);
H4 <= to_signed(3,8);
H5 <= to_signed(1,8);

--multipliers
MCM5 <= H5*Xin;
MCM4 <= H4*Xin;
MCM3 <= H3*Xin;
MCM2 <= H2*Xin;
MCM1 <= H1*Xin;
MCM0 <= H0*Xin;

--adders
add_out1 <= Q1 + MCM4;
add_out2 <= Q2 + MCM3;
add_out3 <= Q3 + MCM2;
add_out4 <= Q4 + MCM1;
add_out5 <= Q5 + MCM0;

--registers
dff1 : DFF port map(Q1,Clk,MCM3);
dff2 : DFF port map(Q2,Clk,add_out1);
dff3 : DFF port map(Q3,Clk,add_out2);
dff4 : DFF port map(Q4,Clk,add_out3);
dff5 : DFF port map(Q5,Clk,add_out4);

process(Clk)
begin
if(rising_edge(Clk)) then
Yout <= add_out5;
end if;
end process;

end Behavioral;