VHDL + SV in UVM in VCS

nyamars · Aug 14, 2013

Can anyone please tell me how to compile VHDL (DUT files) and SV files in UVM environment in VCS?

meir · Aug 14, 2013

3 stages, see vcsmx_ug.pdf for more details
compile:
vhdlan <vhdl design files>
vlogan <verilog design files>
vlogan -ntb_opts uvm (no source files)
vlogan -ntb_opts uvm <sv uvm files>
elaborate:
vcs <top_module>
run:
./simv

VHDL + SV in UVM in VCS

nyamars

Newbie level 2

meir

Junior Member level 3

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VHDL + SV in UVM in VCS

nyamars

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meir

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