VHDL stimuli timing and asserts

[kingslayer]

Dear all,

I am facing a problem while simulating a VHDL design. I am using 'ncvhdl' from Cadence for simulation, and I am trying to use asserts along the simulation. In particular, I have the following code:

-- Standard includes
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use IEEE.STD_LOGIC_ARITH.ALL;

-- Work includes
use work.all;
use work.e3_utils.all;

-- Miscellanea includes
use std.TextIO.all;

entity adder_TB is
end adder_TB;

architecture Simulation of adder_TB is
	component adder
		port(
			operand_l_i : in std_logic;
			operand_r_i : in std_logic;
			carry_i : in std_logic;
			result_o : out std_logic;
			carry_o : out std_logic
		);
	end component adder;

	-- Input stimuli
	signal a : std_logic := '0';
	signal b : std_logic := '0';
	signal c : std_logic := '0';

	-- Output signals
	signal result : std_logic;
	signal carry : std_logic;
begin
	-- Prepare stimuli
	STIMULI_GENERATOR : process is
	begin
		a <= '1'; -- (1)
		assert (result='1' and carry='0') -- (2)
			report "[E@adder] Circuit failure at: (" & std_logic'image(a) &
				"," & std_logic'image(b) & "," & std_logic'image(c) & ")=(" & 
				std_logic'image(result) & "," & std_logic'image(carry) & ")"
			severity Error;

		-- End simulation
		assert false report "[SIMEND] End of simulation reached without errors" severity failure;
	end process STIMULI_GENERATOR;

	-- Connect instance
	TOP_INSTANCE_0 : adder
		port map(
			operand_l_i => a,
			operand_r_i => b,
			carry_i => c,
			result_o => result,
			carry_o => carry
		);
end Simulation;

But when I apply the stimulus (1) and check the result at (2), I notice that: the value of 'a' printed by the assertion is '0' and not '1', and both 'result' and 'carry' signals are 'U'. It seems that the simulation at this point has no chance to make 'a' signal stable before the assertion. Indeed, if I introduce

wait until (result'stable and carry'stable)

code, this works well. In this case, however, if I append the following stimuli to the code, the second stimulus is not simulated

		a <= '0'; 
                        b <= '1';
                        c <= '1';
		assert (result='0' and carry='1')
			report "[E@adder] Circuit failure at: (" & std_logic'image(a) &
				"," & std_logic'image(b) & "," & std_logic'image(c) & ")=(" & 
				std_logic'image(result) & "," & std_logic'image(carry) & ")"
			severity Error;

What am I doing wrong?

Thanks all for your help
Best regards