VHDL SPI driver for AD5781

library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
 use IEEE.numeric_std.all;
 
 entity AD5781 is
    Port ( 
 Sync : out std_logic; -- Signal de synchronisation
 Sclk : out std_logic; -- Horloge
 SDin : out std_logic; -- Données à convertir
 SD0  : in std_logic; -- Données de sortie (verification ou daisy chain)
 LDAC : out std_logic; -- Chargement de la valeur à convertir
 CLR  : out std_logic; -- Signal de clear
 
 Clk  : in std_logic; -- horloge fpga
 Data_in : in std_logic_vector(15 downto 0); -- Données d'entrée à convertir
 Addr_ok : in std_logic -- Validation de l'adresse
			        );
 end AD5781;
 
 architecture Driver of AD5781 is

signal Data_to_send : std_logic_vector(23 downto 0);
signal init : natural :=0;
constant max_count : natural := 1000;
signal Rst_n : std_logic;
signal Sclk_temp : std_logic;



begin

Rst_n <= '1';
 
Reception_donnees : process(Data_in, Addr_ok, init)

begin
	if Addr_ok='1' or init=1 then

		Data_to_send <= "0" & "001" & X"3fff" & "00" & "11" ; --  contient les data a envoyer
		--Data_to_send <= "0" & "001" & Data_in & "00" & "11" ; --  contient les data a envoyer
	

	
else 
	
	if init=0 then
	--Data_to_send <= "001000000000000000010010";
	Data_to_send <= "0" & "001" & X"3fff" & "00" & "11" ;
	end if;
	
end if;


	




end process Reception_donnees;

generation_horloge : process(Clk, Rst_n)
variable count : natural range 0 to max_count;
begin

if Rst_n = '0' then
	count := 0;
	--Sclk <= '1';
	Sclk_temp <= '1';
elsif rising_edge(Clk) then
	if count < max_count/2 then
		-- Sclk <= '1';
		 Sclk_temp <= '1';
		 count := count + 1;
	elsif count < max_count then
		-- Sclk <= '0';
 		 Sclk_temp <= '0';
		 count := count + 1;
	else
		 count := 0;
		-- Sclk <= '1';
		 Sclk_temp <= '1';
	end if;
end if;

end process generation_horloge; 

 
emission_donnees : process(Data_to_send, Sclk_temp, init, Clk)
variable i : integer :=23;
variable rep : integer :=0;
begin

LDAC <= '0';
CLR  <= '1';



if rising_edge(Sclk_temp) and i>=0 then

	Sync <= '0';
	SDin <= data_to_send(i);
	Sclk <= '1';
		
end if;

if falling_edge(Sclk_temp) then
		i:=i-1;
		
		if i<0 then
		Sync <='1';
		SDin <='0';
		else
			Sclk <= '0';
		end if;
		
		if i<-2 then
			i:=23;
			Sync <='1';
			SDin <='0';
		end if;

end if;





end process emission_donnees;  
 
end Driver;

CLR  <= '1';

Sclk <= Sclk_temp;

if rising_edge(Sclk_temp) then
	
	if i>=0 then
	LDAC <= '1';
	Sync <= '0';
	SDin <= data_to_send(i);
	
	end if;
	
		i:=i-1;
		
		if i<-1 then
		LDAC <= '0';
		Sync <= '1';

			
			if i<-2 then
			i:=23;
			end if;
		
		end if;
		


end if;