sathishkas
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Hi,
I have written a simple D Flip-flop code and a corresponding test bench in VHDL code. While I compiled I didnt get any warnings/errors. But when I was running VHDL Simulation with NC-Sim I encountered the following error. I need to dump out the waveform and check the output. Should I specify any time scale value in the RTL file. If so, how to specify the timescale value?
Run Command : irun dff.vhd tb_dff.vhd -gui &
Error :
irun: 12.10-s004: (c) Copyright 1995-2012 Cadence Design Systems, Inc.
irun: *E,VHDLTP: VHDL files are being compiled. The utility does not automatically calculate top-level VHDL design units.
Can anyone tell me how to resolve the problem.
I have written a simple D Flip-flop code and a corresponding test bench in VHDL code. While I compiled I didnt get any warnings/errors. But when I was running VHDL Simulation with NC-Sim I encountered the following error. I need to dump out the waveform and check the output. Should I specify any time scale value in the RTL file. If so, how to specify the timescale value?
Run Command : irun dff.vhd tb_dff.vhd -gui &
Error :
irun: 12.10-s004: (c) Copyright 1995-2012 Cadence Design Systems, Inc.
irun: *E,VHDLTP: VHDL files are being compiled. The utility does not automatically calculate top-level VHDL design units.
Can anyone tell me how to resolve the problem.