VHDL simulating a clock that doesn't run all the time

shaiko · Nov 30, 2014

Hello,

Signal x is a simulated clock that's defined as follows:

Code:

signal x : std_logic := '0' ;
x <= not x after 10ns ;

Suppose, I want x to start running after 100ns and stop after 1000ns.
The obvious solution will be to mux it...my question:

Is there a simple simulation syntax that allows to do that without using a mux?

sharath666 · Nov 30, 2014

You can use this.
x <= '0', not x after 100 ns, '0' after 1000 ns;

TrickyDicky · Nov 30, 2014

sharath666 said:
You can use this.
x <= '0', not x after 100 ns, '0' after 1000 ns;

That wont make a clock, that will just set it high for 900 ns.

The easiest option is a mud like you suggested, or a process with control loops.

shaiko · Nov 30, 2014

a process with control loops.

Can you post an example please ?

TrickyDicky · Nov 30, 2014

Code VHDL - [expand]
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Process
Begin
  input <= '0';
  wait for 100ns;
 
  for I in 1 to 90 loop 
    input <= not input;
    wait for 10 ns;
  end loop;
 
 input <= '0';
End process;

FvM · Nov 30, 2014

A terminating wait statement should stop further process schedule.

VHDL simulating a clock that doesn't run all the time

shaiko

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Code VHDL - [expand]
1 2 3 4 5 6 7 8 9 10 11 12	Process Begin input <= '0'; wait for 100ns; for I in 1 to 90 loop input <= not input; wait for 10 ns; end loop; input <= '0'; End process;

VHDL simulating a clock that doesn't run all the time

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