vhdl sdram
Hi Manuel,
Firstival I would recommended go to faster spped you can, ie organize pipe lines and constrain your design
SDARM gives you advantages speed and size compare to SRAM, but you have burst cycles for SDRAM you can burst entire page. It means you need to have FIFO internally in your FPGA
Then How to work with SDRAM: 1 initialize, after it goes into IDLE and from idle you can write or read. you will need to make state machine to handle that. When you are making state machine try to use smaller number of stages , in order to achive better performance.
If you give more details about what are you trying to do I can give you more hints how to implemented
Good lack