[SOLVED] VHDL scope vs visibility vs visibility by selection

Code VHDL - [expand]
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library ieee;
use ieee.std_logic_1164.all;
 
 
entity tb is
    end entity tb;
 
 
architecture ar_tb of tb is
 
    signal a : std_logic_vector(3 downto 0);
 
begin
 
    process is
    begin
        wait for 1 ns;
        a <= x"0";
        wait for 49 ns;
        a <= x"1";
        wait for 97 ns;
        a <= x"2";
        wait for 17  ns;
        a <= x"3";
        wait for 10 ns;
        wait;
    end process;
 
    a_block : block
 
        signal a : std_logic_vector(3 downto 0);
 
    begin
        
        process(ar_tb.a) is -- , work.ar_tb.b_block.b) is -- , ar_tb.b_block.b)
        begin
            if ar_tb.a'event then
                a <= ar_tb.a ;
            end if;
            --if ar_tb.b_block.b'event then
                --a <= ar_tb.b_block.b;
            --end if;
        end process;
 
    end block a_block;
 
    b_block : block
        signal b : std_logic_vector(3 downto 0);
    begin
        process
        begin
            wait for 5 ns;
            b <= X"F";
            wait for 9 ns;
            b <= X"E";
            wait for 99 ns;
            b <= X"9";
            wait;
        end process;
    end block b_block;
    
    process
    begin
        wait for 1 us;
        report "" severity failure;
    end process;
 
end architecture;

Code VHDL - [expand]
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a <= << signal ^.b_block.b : std_logic_vector(3 downto 0) >> ;

Code VHDL - [expand]
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alias b_block_b is << signal ^.b_block.b : std_logic_vector(3 downto 0) >> ;
...
a <= b_block_b;