Sorry for my fisrt answer it's not quite correct.
Z-state is high impedance state of output driver .
Output in Z-state isolated from input, the same situation
when you place resistor 10Mom in series from output to
input. All value from output do not reach input.
Next : you have data_in INOUT bus from FPGA to external world
and data = internal signal.
data_in is bus working in INOUT mode that means input
and output connected together.
Why do you use INOUT bus if it's destination only for INPUT data
(judging on name data_in).If so, use IN mode (ie data_in : IN std_logic_vector..)
If it's not, and you need inout bidirectional bus, well go further.
As i said, INOUT means input pin and output driver connected together.
If there is any value on output driver, that the same value you will see
on input. Driver stronger input, you see output value backward on input,
because they connected together.
If you want to see value from external driver connected to your IO pin on
IO bus data_in, you MUST place your output bus to Z state.
If you will not place your output to Z state in worst case external driver
will be fight with you internal output driver. Win strongest. And you will
see result of this fighting on your input data_in.
When your output placed in Z state your output is isolated from input,
and you will see signal from external driver connected to that pin.
That why you must to use Z-state.
Now your data_in in Z-state and you are waiting correct data from external
driver.
If you permanently assign data<=data_in, that 'data' set to unknown state.
Well it's not problem. When you place external data to data_in, do you
have any signal in external pins, which accompanies with valid data .
If you have, not problem. Test this signal and only when that signal
valid, assign data<=data_in.
If you have not such signal, how FPGA define correct data on data_in bus ?