library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
use ieee.std_logic_textio.all;
entity CARRY_LOOKAHEAD_ADDER_TB is
generic(
VECTOR_LENGTH : natural := 98;
MEMORY_DEPTH : natural := 32;
ADDRESS_WIDTH : natural := 6
);
end entity CARRY_LOOKAHEAD_ADDER_TB;
architecture BEHAVIOURAL of CARRY_LOOKAHEAD_ADDER_TB is
type MEMORY is array (0 to MEMORY_DEPTH - 1) of std_logic_vector(VECTOR_LENGTH - 1 downto 0);
signal CLK : std_logic;
signal TEST_DATA_MEMORY : MEMORY;
signal ADDRESS : natural range 0 to (2**ADDRESS_WIDTH - 1);
signal ADDRESS_NEXT : natural range 0 to (2**ADDRESS_WIDTH - 1);
signal NUMBER_OF_ERRORS : natural range MEMORY_DEPTH - 1 downto 0;
file TEST_DATA: text;
begin
process
begin
CLK <= '1';
wait for 5 ns;
CLK <= '0';
wait for 5 ns;
end process;
CI <= '0';
file_open(TEST_DATA, "cla_tb_v.txt", read_mode);
process
variable TEST_VECTOR : line;
variable MEMORY_WORD : std_logic_vector(VECTOR_LENGTH - 1 downto 0);
begin
while not endfile(TEST_DATA)loop
readline(TEST_DATA, TEST_VECTOR);
read(TEST_VECTOR, MEMORY_WORD);
TEST_DATA_MEMORY(ADDRESS) <= MEMORY_WORD;
end loop;
wait;
end process;
end BEHAVIOURAL;