This is an issue to do with loops and the quirks of VHDL.
When you use a signal inside a for or while loop in VHDL, it has no idea which bits are driven and are not driven in C (age old locally/globally static issues). So it assumes All bits of C are driven from inside the process, even though you know they're not.
So C(0) gets driven from inside and outside the process, causing C(0) to be X, which will propogate all the way through sum and C.
I learned this myself a few weeks ago with exactly the same problem (I raised a ticket to mentor about it - they pointed out the LRM).
You can fix it by putting the C(0) assignement inside the process;