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VHDL Question: case statements

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Smuggl0r

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Hi,
I was just wondering something. If i have a some code like this:

process(CLK)
begin

case Signal is

when SignalCase1 =>
Signal <= SignalCase2;

when SignalCase2 =>
Signal <= SignalCase3;

when SignalCase3 =>
null;

end case;

end process;

Now what this code should do is, on every change of the clock (CLK), if Signal is equal to SignalCase1 then, Signal = SignalCase2, and same for next statement also. Now, say the code got to SignalCase1, and it then set Signal to SignalCase2, would it go straight to the SignalCase2 statement, as that condition is now met? Or would it end the case statement, and wait until the next clock change?
Any help appreciated.
Thanks.

Smuggl0r
 

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