Vhdl question about process(enable) syntax

[tooh83]

Vhdl questions

hi
i have two question
1 -when i write the following lines
process(enable)
begin
if (enable = '0') then
do sth..
it is hardware implemented as a register with enable as a clock input
but i dont want the enable to be a clock

2 - any one knows how to simulate INOUT pins in Quartus II 5.1

thnx for the help

 

[bansalr]

Re: Vhdl questions

The First assumption is not correct.

1. Untill unless the code is written with enable'event and enable = '1' it will not be taken as clock and flifp flop will not be inferred.
2. Other is latch inference if u don't have the else part in design

i.e if enable = '0'
do sth
end if

2. I didn't understand do u want timing simulation ?

 

[tooh83]

Re: Vhdl questions

1) here is a decoder code in which i m using enable and in the attached figure as u can c it is implemented as a register with enable as a clock :
code :
--------
library ieee;
use ieee.std_logic_1164.all;
entity decoder is
port (
enable : in std_logic ;
data : in std_logic_vector( 1 downto 0 );
A0,A1,A2,A3 : out std_logic
);
end decoder;
architecture behave of decoder is
begin
process(enable)
begin
if (enable = '0') then
A0 <= (not data(1)) and (not data(0));
A1 <= (not data(1)) and data(0);
A2 <= (not data(0)) and data(1);
A3 <= data(1) and data(0);
end if;
end process;
end behave;

2)for 2nd question yes i mean timing simulation