vhdl programming for multiplicative inverse inverse modulo 2^4+1

Code VHDL - [expand]
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
entity mulinv is
port(x:in std_logic_vector(3 downto 0);
      z:out std_logic_vector(3 downto 0));
end mulinv;
 
architecture Behavioral of mulinv is
signal xi,zi,t1,t2,y,q:integer;                              
begin
process(x)
begin
xi<=conv_integer(x);
t2<=1;
 if (xi=1) then zi<=1;
 elsif (xi=0) then zi<=0;
 else
   t1<=17/xi;
   y<=17 mod xi;
   if(y=1) then zi<=(1-t1);
    else
        while (y/=1) loop
             q<=xi/y;
            xi<=xi mod y;
             t2<=t2+(q*t1);
             if xi=1 then zi<=t2;
             else  q<=y/xi;
                   y<=y mod xi;
                     t1<=t1+(q*t2);
 
              end if;
             end loop; 
 
         end if;
  zi<=(1-t1);
 end if ;
 
z<=conv_std_logic_vector(zi,4);
end process;    
  
end Behavioral;