VHDL process statement confusion?

I am trying to learn VHDL and struggling with some of its basics. The question is as follows:

Process statement is described to contain code that runs sequentially (one line after the other). I want to ask why can't one run concurrent code in a process statement (means all lines execute in parallel). Secondly, if process statement contains sequential code, how can it model for example, three flip-flops concurrently e.g.,

--inside process statement

Thanks for being an awesome community

This goes to the fundamentals of how VHDL works (and Verilog for that matter). First of all, you need to know the difference between signals and variables:
1. Signals are only updated when a process suspends, and will take the last assignment given to them
2. Variables are updated immediatly.

So for the following two bits of code give different results:


Here, s will increment by 1 on every clock cycle, because it takes the final assignment only, and v will increment by 3 as it's value is updated imediatly.
This is important, as it allows you to model pipelines and other registers inside a clocked process:


so as each signal is only updated when process suspends, each value is assigned the "old" value of the previous signal, meaning you get a pipeline delay of 4 clock between input and output. If you did the same thing with variables:


The output would only have a 1 clock latency, as the variables are all updated immediatly. Just to confuse you more - think about what this does:


Now, also asside from this, the simulation doesnt run in absolute time, it runs in delta cycles. A delta cycle is an infinitesimal time step. Signals are scheduled to update within a specific delta cycle, and a signal assignment takes a single delta to complete. So consider the following unclocked code:


for the input to get to the output will take 4 delta cycles in simulation, as a will update when ip updates, b when a updates, finally propogating through to updating the output. HDL is a language of consequences, so updating one signal will cause other signals to get updated. And because the time step is a single delta, it can model signal propgation through wires, logic etc. The register comes in with a clock - the rising edge of the clock causes the clocked processes to update the signal assignments in them, which in turn will cause any other logic to update if it is unclocked.

The reason we can model flip-flips is that all clocked signals are updated within the same delta. Because the clock then does not rise again for N ns, and clocked processes are only sensitive to the clock, the signals are not updated again until the next clock.

Your 1st question's ans is
if you write
Q1<= D1;
Q2<= D2;
inside the process then these two statements will execute concurrently as the second statement has no dependency on 1st statement and execute on same clock.

your second question is
if you see the hardware implementation of it, it will instantiate flipflops for Q1 and Q2 and the basic Idea behind FF is to store data.
output of Q1 is input of second FF Q2...

I didn't see tricky's post while posting.. it elaborates my point better.

tariq786 said:

I am trying to learn VHDL and struggling with some of its basics. The question is as follows:

Process statement is described to contain code that runs sequentially (one line after the other). I want to ask why can't one run concurrent code in a process statement (means all lines execute in parallel). Secondly, if process statement contains sequential code, how can it model for example, three flip-flops concurrently e.g.,


--inside process statement

Code:

    Q1 <= D1;
    Q2 <= Q1;
    Q3 <= Q2;

Thanks for being an awesome community

Click to expand...

to model sequential statements it can use serial registers(for example)
concurrent code can also be executed inside a process ,but we can write it even without process hence not required and process statement consumes more time and circuit complexity also increases.