VHDL Process sensitivity list

library IEEE; 
use IEEE.Std_logic_1164.all;
use std.textio.all;

entity E1_TB is
end entity E1_TB;

architecture BENCH of E1_TB is 
signal A : Std_logic;
signal B : Std_logic;
signal C : Std_logic;
  
begin 

  process (A, B, C)
  variable var2 : line;
  begin

    
    write(var2, string'("ENTER: At Time = "));
    write(var2, now);
    write(var2, string'(" INPUT  = "));
    write(var2, A);
    write(var2, B);
    write(var2, C);
    writeline(output, var2);

    C <= B after 4 NS;
    B <= A after 10 ns;
    
      write(var2, string'("EXIT: At Time = "));
      write(var2, now);
      write(var2, string'(" iOUT1  = "));
      write(var2, A);
      write(var2, B);
      write(var2, C);
      writeline(output,var2);
  end process;
  
  Stim: process
  begin 
    wait for 1 ns;
    B <= '0'; 
    wait for 25 NS;
    B <= '1';
    wait;
  end process;  
end architecture;