Vhdl process problem. Need help !

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tosunco

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Code VHDL - [expand]
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library ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_ARITH.all;
use IEEE.std_logic_UNSIGNED.all;
use ieee.numeric_std.all;
entity sevenseg is
    port ( sw: in std_logic_vector (7 downto 0);
        clk: in std_logic;
        ssegon: out std_logic_vector(3 downto 0);
        sseg: out std_logic_vector (0 to 6));
end sevenseg;
architecture behavioral of sevenseg is
    signal count : integer :=0;
    signal count2 : integer :=0;
    signal clk_1000hz : std_logic :='0';
    signal a1 : integer range 0 to 9:= 1;
    signal a2 : integer range 0 to 9:= 1;
    signal a3 : integer range 0 to 9:= 1;
    signal a4 : integer range 0 to 9:= 1;
    signal a1_en : std_logic := '1';
    signal a2_en : std_logic := '1';
    signal a3_en : std_logic := '1';
    signal a4_en : std_logic := '1';
    function divide(bolunen, bolen: in integer)
    return integer is
    variable var,count : integer;
begin
 
var:=bolunen;
count:=0;
for i in 0 to 100 loop
 
if (var>=bolen) then
var :=var-bolen;
count:=count+1;
end if;
return count;
end loop;
end divide;
function seven_segment_display(din: in integer)
return std_logic_vector is
variable sev_seg: std_logic_vector(0 to 6);
begin
sev_seg:="0000000";
case din is
when 0=> sev_seg := "0000001";
when 1=> sev_seg := "1001111";
when 2=> sev_seg := "0010010";
when 3=> sev_seg := "0000110";
when 4=> sev_seg := "1001100";
when 5=> sev_seg := "0100100";
when 6=> sev_seg := "0100000";
when 7=> sev_seg := "0001111";
when 8=> sev_seg := "0000000";
when 9=> sev_seg := "0000100";
when others => sev_seg := "1111111";
end case;
return sev_seg;
end seven_segment_display;


process(clk)

Code VHDL - [expand]
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begin
variable converted : integer := 0;
variable var,count_division : integer;
variable a1temp : integer range 0 to 9:= 1;
variable a2temp : integer range 0 to 9:= 1;
variable a3temp : integer range 0 to 9:= 1;
variable a4temp : integer range 0 to 9:= 1;
begin
if(clk'event and clk='1') then
count <=count+1;
if(count = 50000) then--10khz
clk_1000hz <= not clk_1000hz;
count <=1;
end if;
end if;
if(clk_1000hz'event and clk_1000hz='1') then
count2 <=count2+1;
if(count2 = 100) then--10khz
count2 <=0;
end if;
end if;
if(((count2 mod 4)=1) and a1_en='1')then
ssegon <= "0111";
sseg <= seven_segment_display(a1);
end if;
if(((count2 mod 4)=2)and a2_en='1') then
ssegon <= "1011";
sseg <= seven_segment_display(a2);
end if;
if(((count2 mod 4)=3) and a3_en='1')then
ssegon <= "1101";
 
sseg <=seven_segment_display(a3);
end if;
if(((count2 mod 4)=0)and a4_en='1') then
ssegon <= "1110";
sseg <= seven_segment_display(a4);
end if;
converted:=conv_integer(sw);
count_division:=0;
for i in 0 to 2 loop
if (converted>=100) then
converted :=converted-100;
count_division:=count_division+1;
else
a2temp:=count_division;
end if;
end loop;
count_division:=0;
for i in 0 to 10 loop
if (converted >=10) then
converted :=converted-10;
count_division:=count_division+1;
else
a3temp:=count_division;
end if;
end loop;
a2<=a2temp;
a3<=a3temp;
a4<=converted;
end if;
end process;



When I run my code, I'm getting an error at the line 63 which is underlined and bolded.
It says "Line 63. parse error, unexpected PROCESS"

Can anyone please help to solve this problem?
 
Last edited by a moderator:

I'll take a guess that line 63 is

process(clk)

If so, the problem is that there is no 'begin' before the process to mark the beginning of the architecture code. What you have is:

Code: 
architecture ...
  functions...
  process
  begin...
But it should be

Code: 
architecture ...
  functions...
begin
  process
  begin...
 

K-J thank you for reply. Actually I wrote it with "begin" but the program gave me more than one error about my variable "converted" I defined this variable but It says "undefined symbol" and "unexpected variable" for all the lines which have "converted"
 

Next time use the syntax tags. Reformatting poorly written code is tedious at best. Learn to format your code it's pretty much unreadable as is without any white space above and below blocks of code.

You don't seem to know any of the syntax for VHDL, maybe you should learn the syntax for a process before writing code.

You wrote this, which is incorrect.
Code VHDL - [expand]
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process(clk)
begin
  variable converted : integer := 0;
begin

You should only have a begin after the variable declarations:
Code VHDL - [expand]
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process(clk)
  variable converted : integer := 0;
begin


You have an unsynthesizable construct in your process:
Code VHDL - [expand]
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process(clk)
    -- your variable declarations
  begin
    if(clk'event and clk='1') then
      count <=count+1;
      if(count = 50000) then--10khz
        clk_1000hz <= not clk_1000hz;
        count <=1;
      end if;
    end if;
 
    if(clk_1000hz'event and clk_1000hz='1') then
      count2 <=count2+1;
      if(count2 = 100) then--10khz
        count2 <=0;
      end if;
    -- etc.

Generating a clock (clk_1000hz) and using it in the same process is both unsynthesizable and is a very poor design practice. Even if you separated the generated clock into its own process you would still have the issue of generating a clock from a register and routing it to a clock buffer which even the FPGA vendors suggest NOT doing that.

You also are using a bunch of variables, which can be a problem if you don't know what logic will be generated from a synthesis tool. I'm not an expert on VHDL and variables, but I suspect the following code won't turn out as you expected.
Code VHDL - [expand]
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converted:=conv_integer(sw);
    count_division:=0;
    for i in 0 to 2 loop
      if (converted>=100) then
        converted :=converted-100;
        count_division:=count_division+1;
      else
        a2temp:=count_division;
      end if;
    end loop;
    count_division:=0;
    for i in 0 to 10 loop
      if (converted >=10) then
        converted :=converted-10;
        count_division:=count_division+1;
      else
        a3temp:=count_division;
      end if;
    end loop;


Besides that you have a mismatch between the opening if and the end if;
And you are missing the end behavioral;, that ends your architecture.

Regards

- - - Updated - - -

As I was curious I threw the code into Vivado synthesis after fixing the problems and NOT separating the two clocked processes (amazingly Vivado synthesis didn't complain about having two clocks in the process) and ended up with the following schematic of the design.


As is apparent, poorly written code results in poor results...
The light purple is the converted signal.
The blue is the clk
The red is the generated clk_1000hz

As is obviously apparent the converted isn't even clocked it's a big combinatorial "blob" with a much bigger combinatorial "blob" following it before it ends up at a register on the far far far lower right side.

Draw a schematic of what you want and make a VHDL (hardware description) that implements your drawing.

Regards
 
Last edited:

Generating a clock (clk_1000hz) and using it in the same process is both unsynthesizable and is a very poor design practice.
Click to expand...
Bad design practice - probably, synthesizable - though.
 

FvM said:
Bad design practice - probably, synthesizable - though.
Click to expand...

Well you're right it does synthesize, but there could be a mismatch between synthesis and the simulation as the generated clock wasn't in the process sensitivity list.
 

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