[VHDL] problem during the simulation -- solved

[emefes]

Hello everybody,

I work on a pipeline whose stages are described using processes. I want to 'transform' these processes into entities which is kinda easy to do. Until then, no problem even when I compile my beautiful work
But the weird stuff happens when I simulate it. Two of the five stages disappeared (in the project hierarchy). I checked out that they were correctly compiled and they are. Of course I also verified that I correctly instantiated the components and I think I did...
Does anyone know what could make this kind of problem happen ?

 

[shiva_mag]

Re: [VHDL] problem during the simulation

which tool are u using?

 

[emefes]

Re: [VHDL] problem during the simulation

I am using Modelsim SE 5.8.


-- edit :
It was a fu**ing entity name problem. Modelsim doesn't like entities named decode or memory. I'll remember it