VHDL, Prefix of attribute 'left must be an array object.

Hi all, I have been trying to debug the code for almost a week, and I have got nothing, please help me............
THE ERROR IS IN THE ASSERT PART THE ERROR IS AS SHOWN "Prefix of attribute 'left must be an array object." PLEASE HELP ME OUT ...
THE CODE IS SHOWN BELOW, THIS CODE IS FROM PEDRONI FROM CHAPTER FUNCTION AND PROCEDURES....


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
use IEEE.NUMERIC_STD.ALL;

entity comparator is
port (a,b,c: in integer range 0 to 255;
y: out integer range 0 to 255);
end comparator;

architecture comparator of comparator is
function max (in1,in2,in3: integer) return integer is
begin
----check in-out signals-----------------------------

assert(y'left=a'left and y'left=b'left and y'left=c'left and
y'right=a'right and y'right=b'right and y'right=c'right)
report "signal sizes are not all equal!"
severity error;
----find maximum--------------------------------------
if (in1>=in2 and in1>=in3) then
return in1;
elsif (in2>=in3 and in2>=in1) then
return in2;
else
return in3;
end if;
end function;
begin
y<= max(a,b,c);--positinal mapping
end Behavioral;

According to VHDL specification, the predefined attribute 'left can be applied to integer type. Apparently this isn't supported by your synthesis tool or simulator.

Thanks a lot, but I have Xilinx 14.6 with ISE webpack license, could it be that it is not supported ........ please tell me if there is any way to solve this issue ..........

You can try 'high and 'low attributes instead.