A
ahmadagha23
Guest
Hi
I want to simulate my maped vhdl code synthesized by synplifypro7.5.1 (*.vhm filecreated by synplify) but when I compile the synplify.vhd file (that is needed for simulation of *.vhm code) by ModelSim it get error (on line 128 and 304 of synplify.vhd code)but the code is true and when I compile it by ActivHDL it compiled with no errors.
Why some times a vhdl code that is comiled truely by ActivHDL not compiled (get errors) by modelsim?
please help me.
for more information search modelsim third party software in synplify help.
thanks alot
I want to simulate my maped vhdl code synthesized by synplifypro7.5.1 (*.vhm filecreated by synplify) but when I compile the synplify.vhd file (that is needed for simulation of *.vhm code) by ModelSim it get error (on line 128 and 304 of synplify.vhd code)but the code is true and when I compile it by ActivHDL it compiled with no errors.
Why some times a vhdl code that is comiled truely by ActivHDL not compiled (get errors) by modelsim?
please help me.
for more information search modelsim third party software in synplify help.
thanks alot