Aya2002
Advanced Member level 4
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Hello Friends,
Kindly, I am writing a code for FIFO - RAM to use it with my UART controller. Now I got the code for the first part which is the FIFO + RAM. In fact it is not my code, I found it on the net which is as follows:
and
and the RAM2 is
the Quartus II gave me the following error:
Error (10344): VHDL expression error at FIFO.vhdl(39): expression has 3 elements, but must have 5 elements
I think I do not have a problem in my code but I am not expert. I hope somebody can help me.
Thank you very much
Kindly, I am writing a code for FIFO - RAM to use it with my UART controller. Now I got the code for the first part which is the FIFO + RAM. In fact it is not my code, I found it on the net which is as follows:
Code:
library IEEE;
library work;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use work.all;
entity FIFO is
generic (N: integer := 3; -- number of address bits for 2**N address locations
M: integer := 5); -- number of data bits to/from FIFO
port (CLK, PUSH, POP, INIT: in std_logic;
DIN: in std_logic_vector(N-1 downto 0);
DOUT: out std_logic_vector(N-1 downto 0);
FULL, EMPTY, NOPUSH, NOPOP: out std_logic);
end entity FIFO;
architecture TOP_HIER of FIFO is
signal WE: std_logic;
signal A: std_logic_vector(N-1 downto 0);
component FIFO_LOGIC is
generic (N: integer); -- number of address bits
port (CLK, PUSH, POP, INIT: in std_logic;
ADD: out std_logic_vector(N-1 downto 0);
FULL, EMPTY, WE, NOPUSH, NOPOP: buffer std_logic);
end component FIFO_LOGIC;
component RAM2 is
generic (K, W: integer); -- number of address and data bits
port (WR: in std_logic; -- active high write enable
ADDR: in std_logic_vector (W-1 downto 0); -- RAM address
DIN: in std_logic_vector (K-1 downto 0); -- write data
DOUT: out std_logic_vector (K-1 downto 0)); -- read data
end component RAM2;
begin
-- example of component instantiation using positional notation
FL: FIFO_LOGIC generic map (N)
port map (CLK, PUSH, POP, INIT, A, FULL, EMPTY, WE, NOPUSH, NOPOP);
-- example of component instantiation using keyword notation
R: RAM2 generic map (W => N, K => M)
[B][U]port map (DIN => DIN, ADDR => A, WR => WE, DOUT => DOUT);[/U][/B]
end architecture TOP_HIER;
and
Code:
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity FIFO_LOGIC is
generic (N: integer := 3);
port (CLK, PUSH, POP, INIT: in std_logic;
ADD: out std_logic_vector(N-1 downto 0);
FULL, EMPTY, WE, NOPUSH, NOPOP: buffer std_logic);
end entity FIFO_LOGIC;
architecture RTL of FIFO_LOGIC is
signal WPTR, RPTR: std_logic_vector(N-1 downto 0);
signal LASTOP: std_logic;
begin
SYNC: process (CLK) begin
if (CLK'event and CLK = '1') then
if (INIT = '1') then -- initialization --
WPTR <= (others => '0');
RPTR <= (others => '0');
LASTOP <= '0';
elsif (POP = '1' and EMPTY = '0') then -- pop --
RPTR <= RPTR + 1;
LASTOP <= '0';
elsif (PUSH = '1' and FULL = '0') then -- push --
WPTR <= WPTR + 1;
LASTOP <= '1';
end if; -- otherwise all Fs hold their value --
end if;
end process SYNC;
COMB: process (PUSH, POP, WPTR, RPTR, LASTOP, FULL, EMPTY) begin
-- full and empty flags --
if (RPTR = WPTR) then
if (LASTOP = '1') then
FULL <= '1';
EMPTY <= '0';
else
FULL <= '0';
EMPTY <= '1';
end if;
else
FULL <= '0';
EMPTY <= '0';
end if;
-- address, write enable and nopush/nopop logic --
if (POP = '0' and PUSH = '0') then -- no operation --
ADD <= RPTR;
WE <= '0';
NOPUSH <= '0';
NOPOP <= '0';
elsif (POP = '0' and PUSH = '1') then -- push only --
ADD <= WPTR;
NOPOP <= '0';
if (FULL = '0') then -- valid write condition --
WE <= '1';
NOPUSH <= '0';
else -- no write condition --
WE <= '0';
NOPUSH <= '1';
end if;
elsif (POP = '1' and PUSH = '0') then -- pop only --
ADD <= RPTR;
NOPUSH <= '0';
WE <= '0';
if (EMPTY = '0') then -- valid read condition --
NOPOP <= '0';
else
NOPOP <= '1'; -- no red condition --
end if;
else -- push and pop at same time –
if (EMPTY = '0') then -- valid pop --
ADD <= RPTR;
WE <= '0';
NOPUSH <= '1';
NOPOP <= '0';
else
ADD <= wptr;
WE <= '1';
NOPUSH <= '0';
NOPOP <= '1';
end if;
end if;
end process COMB;
end architecture RTL;
and the RAM2 is
Code:
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity RAM2 is
generic (K: integer:=8; -- number of bits per word
W: integer:=8); -- number of address bits
port ( WR: in std_logic; -- active high write enable
ADDR: in std_logic_vector (W-1 downto 0); -- RAM address
DIN: in std_logic_vector (K-1 downto 0); -- write data
DOUT: out std_logic_vector (K-1 downto 0)); -- read data
end entity RAM2;
architecture RAMBEHAVIOR of RAM2 is
subtype WORD is std_logic_vector ( K-1 downto 0); -- define size of WORD
type MEMORY is array (0 to 2**W-1) of WORD; -- define size of MEMORY
signal RAM256: MEMORY; -- define RAM256 as signal of type MEMORY
begin
process (WR, DIN, ADDR)
variable RAM_ADDR_IN: integer range 0 to 2**W-1; -- to translate address to integer
variable STARTUP: boolean :=true; -- temporary variable for initialization
begin
if (STARTUP = true) then -- for initialization of RAM during start of simulation
RAM256 <= (0 => "00000101", -- initializes first 5 locations in RAM
1 => "00110100", -- to specific values
2 => "00000110", -- all other locations in RAM are
3 => "00011000", -- initialized to all 0s
4 => "00000011",
others => "00000000");
DOUT <= "XXXXXXXX"; -- force undefined logic values on RAM output
STARTUP :=false; -- now this portion of process will only execute once
else
RAM_ADDR_IN := conv_integer (ADDR); -- converts address to integer
if (WR='1') then -- write operation to RAM
RAM256 (RAM_ADDR_IN) <= DIN ;
end if;
DOUT <= RAM256 (RAM_ADDR_IN); -- always does read operation
end if;
end process;
end architecture RAMBEHAVIOR;
the Quartus II gave me the following error:
Error (10344): VHDL expression error at FIFO.vhdl(39): expression has 3 elements, but must have 5 elements
I think I do not have a problem in my code but I am not expert. I hope somebody can help me.
Thank you very much