VHDL Parameter declaration

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hareeshP

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hi,
below is the verilog code 

Code Verilog - [expand]
1

parameter   RST_hold_time = 32'd16384 ;


can we define the above in vhdl like this??

Code VHDL - [expand]
1

constant RST_hold_time  : real := 16384
 

Why are you using a real constant in place of a Verilog unsigned value with width specification? An unsigned or integer constants seems more suitable at first sight.

Secondly your real constant involves a syntax error.
16384.0 would be a valid real value.

Suggest to pre check your VHDL code ideas with a compiler or simulator tool before posting.
 

A verilog parameter (that translates to a "module parametrization value") can be translated into an architecture-local constant. In most cases, generics on entities are probably a closer match, however (as these are used to parametrize these entities at instantiation time).
 

It really depends on the the application, as FvM has pointed out in #2.

constant RST_hold_time : integer range 0 to 16384 := 16384 ;

Declaring it as unsigned will have more flexibility.

As I have been seeing some of your recent posts:
1. Learn one language thoroughly before attempting VHDL <--> Verilog conversions.
2. There are tools/sw for compiling/simulating RTL. Use it! Please stop using EDA board as the compiler.
 
dpaul said:
As I have been seeing some of your recent posts:
1. Learn one language thoroughly before attempting VHDL <--> Verilog conversions.
2. There are tools/sw for compiling/simulating RTL. Use it! Please stop using EDA board as the compiler.
Click to expand...

I've already pointed #1 out in one of their other threads.

As you indicated previously you are learning VHDL, so stop posting Verilog code that you want to convert. You should not even be looking at Verilog code. What you are doing is making it harder to learn VHDL by confusing yourself. e.g. you have regularly used the wrong language syntax when posting code samples, some_bus(2:3) a mix of VHDL and Verilog syntax.
 
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