billkas
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Hello everyone,
Is there a way to create a simulation output file in VHDL? I'm using Modelsim.
So far I've only found something about a TEXTIO package, but I'm not quite sure on how to integrate this into my testbench code (Google didn't help enough this time :-| )
Any advice would be valuable. Thank you!
Is there a way to create a simulation output file in VHDL? I'm using Modelsim.
So far I've only found something about a TEXTIO package, but I'm not quite sure on how to integrate this into my testbench code (Google didn't help enough this time :-| )
Any advice would be valuable. Thank you!