OvErFlO
Full Member level 3
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vhdl conv_integer with select
Can I see with Modelsim state of my FSM, if state is :
architecture
type state_t is (st0, st1, st2 st3);
signal state : state_f;
?
How can I write my ports entity, if my signal is TYPE OF ???
thanks
Can I see with Modelsim state of my FSM, if state is :
architecture
type state_t is (st0, st1, st2 st3);
signal state : state_f;
?
How can I write my ports entity, if my signal is TYPE OF ???
thanks