Vhdl model for single d-type latch with 3-state output

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Hello all. I'm new to VHDL programming so please forgive me in advance if i ask any bad question. I have an assignment to create a VHDL model and testbench for SINGLE D-TYPE LATCH WITH 3-STATE OUTPUT device. I have started reading up as much as i can and time is running out. Could i get ideas, advice or any help on this topic? thanks
 

3 states from a single flip flop? 1, 0 and what else? Z?
WHat code have you got so far? (Btw, only 1 and 0 are feasible inside an FPGA flip flop).
 

OK, that is the problem statement...
Could i get ideas, advice or any help on this topic? thanks
Click to expand...
Yes you can. Now if you ask a more specific question, you can get a more specific answer.

However, if your question is essentially 'Can you post the code for a single d-type latch with 3-state output'?, then the answer you are likely to get is 'No.' Asking such a question indicates that you really don't want to do any work, instead you want someone else to do it for you. If you instead post what code you have and what exactly you are having trouble with, then you'll likely get useful answers. So my advice to you is to post something showing your work and ask targeted questions.

Kevin Jennings
 

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