VHDL "inout" port map connection between two modules

ENTITY RAM IS

PORT (address :in std_logic_vector (15 downto 0);-
- address Input
data :inout std_logic_vector (15 downto 0); --data bi-directional

);
END ENTITY;

PORT (STin : IN std_logic_vector; --Input Data
reset, clk, push, pop : IN std_logic; -- Reset, Clock, Push,and Pop Signals
STout : OUT std logic vector -- Output Data

END ENTITY;

SP_RAM_controler : component SP_RAM
            port map(
                         
		data => STin,
		data => STout,
		
               );

 Cannot assign to object "STin" of mode IN.

if ( cs = '1') then -- must be equal to one in order to make changes on the RAM

	if (oe = '1') then -- read operation (POP)

		--temp:=to_integer(unsigned(address));
		data <= ram(to_integer(unsigned(address)));
		
	elsif (rw = '1' and oe = '0')then -- write operation (PUSH)
		
		ram(to_integer(unsigned(address)))<= data ;
				
	end if;
else 
	data <= (others=>'Z');
end if;

data <= ram(to_integer(unsigned(address)));