vhdl implementation of discrete time pll

Status
Not open for further replies.
K

kumarravi0086

Newbie level 4
Joined
Sep 14, 2010
Messages
6
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Location
india
Activity points
1,327
hi everyone,
i am working vhdl implementation of discrete time pll i have coded phase detector basad on analytic signal,loop filter and dds in vhdl now i want to implement the pll on fpga so i want to connect these component how can i connect these in one program
please help me its urgent,,,,,,,,,,,,,,,


thanks @ regard
Ravi kumar
india
kumarravi0086@gmail.com
 

Status
Not open for further replies.

Similar threads

Menu
Log in
Register
Cookies are required to use this site. You must accept them to continue using the site. Learn more…