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| library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity AES_128_DECRYPT is
Port ( SYS_CLK,RST : in STD_LOGIC;
DECRY_IN : in STD_LOGIC_VECTOR (127 downto 0);
KEY_IN : in STD_LOGIC_VECTOR (127 downto 0);
START : in STD_LOGIC;
KEY_LOAD : in STD_LOGIC;
NEAR_DONE : out STD_LOGIC;
DONE : out STD_LOGIC;
BUSY : out STD_LOGIC;
DECRY_OUT : out STD_LOGIC_VECTOR (127 downto 0));
end AES_128_DECRYPT;
architecture Behavioral of AES_128_DECRYPT is
----Sub Components Definitions
COMPONENT Key_Schedule_128
PORT(
SYS_CLK : IN std_logic;
RST : IN std_logic;
KEY_128 : IN std_logic_vector(127 downto 0);
LOAD_KEY : IN std_logic;
EXP_KEY : IN std_logic;
PAR_KEY : OUT std_logic_vector(127 downto 0)
);
END COMPONENT;
COMPONENT InvSubBytes
Port ( invSubBytes_IN : in STD_LOGIC_VECTOR (127 downto 0);
invSubBytes_OUT : out STD_LOGIC_VECTOR (127 downto 0);
SYS_CLK,RST : in STD_LOGIC);
END COMPONENT;
COMPONENT InvShiftRows
PORT(InvShiftRows_In : in STD_LOGIC_VECTOR (127 downto 0);
InvShiftRows_Out : out STD_LOGIC_VECTOR (127 downto 0);
Sys_Clk,RST : in STD_LOGIC);
END COMPONENT;
COMPONENT InvMixColumns
PORT(
SYS_CLK : IN std_logic;
RST : IN std_logic;
DATA_IN : IN std_logic_vector(127 downto 0);
DATA_OUT : OUT std_logic_vector(127 downto 0)
);
END COMPONENT;
COMPONENT AddRoundKey
PORT(
Data_IN : IN std_logic_vector(127 downto 0);
Key_IN : IN std_logic_vector(127 downto 0);
SYS_CLK : IN std_logic;
RST : IN std_logic;
Data_OUT : OUT std_logic_vector(127 downto 0)
);
END COMPONENT;
----End Sub Components Definitions
type state is (RESET_1,RESET_2,IDLE,PROCESSING);
signal pr_state,nx_state : state ;
SIGNAL RST_BUF : STD_LOGIC := '0';
SIGNAL BUSY_BUF : STD_LOGIC := '0';
SIGNAL DECRY_IN_BUFFER : STD_LOGIC_VECTOR(127 downto 0) := (OTHERS => '0');
SIGNAL OPN_COUNT : STD_LOGIC_VECTOR(1 downto 0) := "00";
SIGNAL RND_COUNT : STD_LOGIC_VECTOR(3 downto 0) := "0000";
SIGNAL RND_MUX_CNTRL : STD_LOGIC_VECTOR(1 downto 0) := "00";
SIGNAL KEY_BUF : STD_LOGIC_VECTOR(127 downto 0) := (OTHERS => '0');
SIGNAL InvSubBytes_IN_BUF : STD_LOGIC_VECTOR(127 downto 0) := (OTHERS => '0');
SIGNAL InvSubBytes_OUT_BUF : STD_LOGIC_VECTOR(127 downto 0) := (OTHERS => '0');
SIGNAL InvShiftRows_IN_BUF : STD_LOGIC_VECTOR(127 downto 0) := (OTHERS => '0');
SIGNAL InvShiftRows_OUT_BUF : STD_LOGIC_VECTOR(127 downto 0) := (OTHERS => '0');
SIGNAL InvMixColumns_IN_BUF : STD_LOGIC_VECTOR(127 downto 0) := (OTHERS => '0');
SIGNAL InvMixColumns_OUT_BUF : STD_LOGIC_VECTOR(127 downto 0) := (OTHERS => '0');
SIGNAL AddRoundKey_IN_BUF : STD_LOGIC_VECTOR(127 downto 0) := (OTHERS => '0');
SIGNAL AddRoundKey_OUT_BUF : STD_LOGIC_VECTOR(127 downto 0) := (OTHERS => '0');
begin
--Instantiate Sub-Components
INST_Key_Schedule_128: Key_Schedule_128 PORT MAP(
SYS_CLK => SYS_CLK,
RST => RST_BUF,
KEY_128 => KEY_IN,
PAR_KEY => KEY_BUF,
LOAD_KEY => KEY_LOAD,
EXP_KEY => BUSY_BUF
);
INST_InvShiftRows: InvShiftRows PORT MAP(
invShiftRows_In => InvShiftRows_IN_BUF,
invShiftRows_Out => InvShiftRows_OUT_BUF,
Sys_Clk => SYS_CLK,
RST => RST_BUF
);
INST_invSubBytes: invSubBytes PORT MAP(
invSubBytes_IN => InvSubBytes_IN_BUF,
invSubBytes_OUT => InvSubBytes_OUT_BUF,
SYS_CLK => SYS_CLK,
RST => RST_BUF
);
INST_AddRoundKey: AddRoundKey PORT MAP(
Data_IN => AddRoundKey_IN_BUF,
Key_IN => KEY_BUF,
Data_OUT => AddRoundKey_OUT_BUF,
SYS_CLK => SYS_CLK,
RST => RST_BUF
);
INST_InvMixColumns: InvMixColumns PORT MAP(
SYS_CLK => SYS_CLK,
RST => RST_BUF,
DATA_IN => InvMixColumns_IN_BUF,
DATA_OUT => InvMixColumns_OUT_BUF
);
-----END Component Instatiation
STATE_MACHINE_HEAD : PROCESS (SYS_CLK,RST) ----State Machine Master Control
begin
IF (SYS_CLK'event and SYS_CLK='1') then
IF (RST = '1') then
pr_state <= RESET_1;
ELSE
pr_state <= nx_state;
END IF;
END IF;
END PROCESS;
STATE_MACHINE_BODY : PROCESS (SYS_CLK,RST,PR_STATE,START,KEY_LOAD,OPN_COUNT,RND_COUNT) ---State Machine State Definitions
begin
CASE pr_state is
WHEN RESET_1 => --Master Reset State
RST_BUF <= '1';
BUSY_BUF <= '0';
nx_state <= RESET_2;
WHEN RESET_2 => --Extra Reset State to prevent reset glitching
RST_BUF <= '1';
BUSY_BUF <= '0';
nx_state <= IDLE;
WHEN IDLE => --Waiting for Key Load or Data/Start assertion
RST_BUF <= '0';
BUSY_BUF <= '0';
IF (START = '1') then
nx_state <= PROCESSING;
ELSE
nx_state <= IDLE;
END IF;
WHEN PROCESSING => --Enable step/round counters
RST_BUF <= '0';
BUSY_BUF <= '1';
IF (OPN_COUNT = "10" AND RND_COUNT = X"0") then
nx_state <= IDLE;
ELSE
nx_state <= PROCESSING;
END IF;
END CASE;
END PROCESS;
OPERATIONS_COUNTER : PROCESS (SYS_CLK,PR_STATE) ----Counts through each step and each round of cipher sequence, affects data path mux and state machine
begin
IF (SYS_CLK'event and SYS_CLK='1') then
IF (PR_STATE = RESET_1 OR PR_STATE = RESET_2 OR PR_STATE = IDLE) then
OPN_COUNT <= "10"; --Step Counter Starts on 2 to correspond to AddRoundKey step at very start of cipher
RND_COUNT <= "1010";
ELSE
OPN_COUNT <= OPN_COUNT + 1; ---Always increment when processing
IF OPN_COUNT = "11" then ---Decrement at the last step of a round
RND_COUNT <= RND_COUNT - 1;
END IF;
END IF;
END IF;
END PROCESS;
DECRYPT_TEXT_OUTPUT_REGISTER : PROCESS(SYS_CLK,PR_STATE) --Output Latch for decrytext
begin
IF (SYS_CLK'event and SYS_CLK='1') then
IF (PR_STATE = RESET_1 OR PR_STATE = RESET_2) then
DECRY_OUT <= (OTHERS => '0');
ELSIF (OPN_COUNT = "10" AND RND_COUNT = X"0") then
DECRY_OUT <= AddRoundKey_OUT_BUF;
END IF;
END IF;
END PROCESS;
DECRYPT_DONE_SIGNAL_LATCH : PROCESS(SYS_CLK) ----Single Pulse Signal when dercryPted data is complete and output data is valid
begin
IF (SYS_CLK'event and SYS_CLK='1') then
IF (OPN_COUNT = "10" AND RND_COUNT = X"0") then
DONE <= '1';
ELSE
DONE <= '0';
END IF;
END IF;
END PROCESS;
NEARLY_DONE_SIGNAL_LATCH : PROCESS(SYS_CLK) -----Single Pule Signal when decrypted data is one clock cycle from completion: possiible trigger for continous loading
begin
IF (SYS_CLK'event and SYS_CLK='1') then
IF (OPN_COUNT = "01" AND RND_COUNT = X"0") then
NEAR_DONE <= '1';
ELSE
NEAR_DONE <= '0';
END IF;
END IF;
END PROCESS;
DATA_PATH_MUX_CONTROL : PROCESS(SYS_CLK,PR_STATE)
begin
IF (SYS_CLK'event and SYS_CLK='1') then
IF (PR_STATE = RESET_1 OR PR_STATE = RESET_2 OR PR_STATE = IDLE) then
AddRoundKey_IN_BUF <= DECRY_IN_BUFFER;
else
AddRoundKey_IN_BUF <= InvSubBytes_OUT_BUF;
END IF;
END IF;
END PROCESS;
counter : PROCESS(SYS_CLK)
begin
IF (SYS_CLK'event and SYS_CLK='1') then
IF (OPN_COUNT = "00" AND RND_COUNT = X"9") then
InvShiftRows_IN_BUF <= AddRoundkey_OUT_BUF;
else
InvShiftRows_IN_BUF <= InvMixcolumns_OUT_BUF;
end if;
end if;
END PROCESS;
Decry_INPUT_REGISTER : PROCESS(SYS_CLK)
begin
IF (SYS_CLK'event and SYS_CLK='1') then
IF (RST = '1') then
DECRY_IN_BUFFER <= (OTHERS => '0');
ELSIF (START = '1' AND PR_STATE = IDLE) then
DECRY_IN_BUFFER <= DECRY_IN;
END IF;
END IF;
END PROCESS;
-----Set Core to Look BUSY during reset without actually asserting BUSY_BUF
BUSY_OUTPUT_MUX : PROCESS (BUSY_BUF,pr_state)
begin
IF (PR_STATE = RESET_1 OR PR_STATE = RESET_2) then
BUSY <= '1';
ELSE
BUSY <= BUSY_BUF;
END IF;
END PROCESS;
---Fixed Pipeline Connections
InvSubBytes_IN_BUF <= InvShiftRows_OUT_BUF;
InvMixColumns_IN_BUF <= AddRoundKey_OUT_BUF;
-----END Async Signals-------------------
end Behavioral; |