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[VHDL] How can I use assertions inside of packages?

Thread starter ivlsi
Start date Jan 29, 2015

Status: Not open for further replies.

Jan 29, 2015

#1

ivlsi

Advanced Member level 3

Hi All,

Is it possible to use VHDL assertions inside of packages? How? Could somebody provide an example?

Thank you!

Status: Not open for further replies.

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