library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
entity ServoTester is
Port ( clr : in STD_LOGIC;
Clk : in STD_LOGIC;
ButtonLeft1 : in STD_LOGIC;
ButtonRight1 : in STD_LOGIC;
pwm : out STD_LOGIC
);
end ServoTester;
architecture Behavioral of ServoTester is
signal count : STD_LOGIC_VECTOR(19 downto 0);
signal duty : STD_LOGIC_VECTOR (19 downto 0) := "00000000000000000000";
signal period : STD_LOGIC_VECTOR (19 downto 0) := "11110100001001000000";
begin -- Period set to 20 ms
proc_clk: process(clk, clr)
begin -- Count increments from zero to period, then resets to zero
if clr = '1' then
count <= (others => '0');
elsif rising_edge(clk) then
if count = period - 1 then
count <= (others => '0');
else
count <= count+1;
end if;
end if;
end process;
process(clk)
begin -- Duty set to user specifications
if rising_edge(clk) then
if ButtonLeft1 = '1' then -- Button Number 3
duty <= "00011001101000101000"; -- 2.1 ms
elsif ButtonRight1 = '1' then -- Button Number 2
duty <= "00001010111111001000"; -- 0.9 ms
else
duty <= "00010010010011111000"; -- 1.5 ms
end if;
end if;
end process;
process(clk)
begin -- Sets Servo signal "High" for all values of count less then duty
if rising_edge(clk) then
if count < duty then
pwm <= '1';
else
pwm <= '0';
end if;
end if;
end process;
end Behavioral;