@trickydicky:
Thanks a lot. I tried adding the reset, but realised i was adding another complication. i thought i could without adding it.
I'm posting the modified code, but i'm experiencing another challenge..
This is the modified code.
entity final_packet_format_error_detection is
port (
data_receive: in STD_LOGIC_VECTOR(0 to 7);
clock : in STD_LOGIC;
special_byte : in STD_LOGIC_VECTOR(0 to 7);
no_of_bytes: in integer range 0 to 1024;
no_error_bytes : inout integer range 0 to 1024 ;
no_special_bytes : inout integer range 0 to 1024 ;
byte_count : inout integer range 0 to 1024
);
end final_packet_format_error_detection;
architecture Behavioral of final_packet_format_error_detection is
type statetype is (START_DETECTION, ANALYZE_DATA);
signal state, next_state: statetype;
begin
operation: process(state, data_receive, special_byte, no_error_bytes, no_special_bytes, clock )
begin
if (clock'event and clock='1') then
case state is
when START_DETECTION => if(data_receive = special_byte) then
state <= ANALYZE_DATA;
else
state <= START_DETECTION;
byte_count <= byte_count + 1;
end if;
when ANALYZE_DATA =>
if(byte_count = no_of_bytes) then
no_special_bytes <= no_special_bytes + 1;
byte_count <= 0;
state <= START_DETECTION;
else
no_special_bytes <= no_special_bytes + 1;
no_error_bytes <= no_error_bytes + 1;
byte_count <= 0;
state <= START_DETECTION;
end if;
end case;
end if;
end process;
end Behavioral;
I want the state transitions to take place in one clock cycle. Presently, it changes state at each rising edge. The problem with this is that by the time it does into the analyze_data state, the data value of byte_count has already changed. Hence, it isn't doing the designated function.