VHDL generate port map issue

Hi,

I have the code below which as far I can work out should be connecting a number of components together in a chain, a bit like a ripple carry, but this for a comparator, with MSB first. Is the syntax correct because it does work, if I synthesize the code to see what circuit I get, it seems to create only one comp (LSB), as if its ignoring the other IF statements? I'm just trying link the previous components ports to the next in a particular order?

The msbslice component has AIH,AIL bit, A,B vectors 15, AOG,AOL bit OUT for reference.

M1: for i in 0 to 15 generate

begin

MSB: if i = 15 generate --MSB
comp: component msbslice
port map (AOGc(i),AOLc(i),AI(i) ,BI(i),AOGc(i-1),AOLc(i-1));
end generate MSB;
LSB: if i = 0 generate --LSB
comp1: component msbslice
port map (AOGc(i),AOLc(i),AI(i),BI(i),AOG, AOL);
end generate LSB;
ALB: if i < 15 and i > 0 generate
comp2: component msbslice
port map (AOGc(i+1),AOLc(i+1),AI(i),BI(i),AOGc(i-1),AOLc(i-1));
end generate ALB;

end generate M1;

I have no idea on the port definitions for all these components. So I have no idea. The if statement wont be ignored. If the layout is not as you expected, then you probably made a mistake.

Post the full code.

Thanks,

I finally got it to work. I had the signal declaration for the internal link inside the for generate loop, I moved this outside into the architecture body and its working. Thanks for the clarification on the If statements though.

J