[SOLVED] VHDL Functions

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clros

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Hi to all,

I am mainly a software developer and I do not old with VHDL.

I have a doubt with functions in VHDL.

I wrote my complex function in vhdl (with some for..cycle internal) and I "recall" this function from my VHDL code, when I am in a determinate state of a my FSM.


My function is circuitly complex: if I view the RTL generated, its have many stages with many MUX and adder. I don't think tath my function end its work in only one clock cycle.
This is a problem for my FSM; how I can understand when my "function" ends? Can I to have a "signal" from my function when it ends for understand when I can to pass to another state of my FSM?
 

A function is comprised of combinational code without a clock and registers. If the data path is longer than the interval between launch and latch clock of the embedding registers, design timing closure will fail.
 

For "software guys" there is a high level synthesis solutions, e.g. HLS from Xilinx. Take a look at HLS and SDSoC software for example. I don't know if there is the license free of cost now.
 
As a software coder you have to understand that what you are designing is hardware not software. Leave the software paradigm behind and think in terms of 7400 series ICs and wires. Learn what structures in VHDL are synthesized to those parts to be able to code something that will actually make timing.

IMO VHDL n00bs should stay away from using functions, for loops, and generate until they are very familiar with how basic stuff like process, if-elsif, case, when, etc are synthesized. Then when you write a function you'll know how much logic you can get away with.
 
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