robmar
Newbie level 3
Hello, I'm a beginner at VHDL. I couldn't find an answer to this online:
What is the difference between using the for generate and for loop when performing signal assignments?
EX:
Thank you!
What is the difference between using the for generate and for loop when performing signal assignments?
EX:
Code:
for i in 0 to 7 generate
a(i) <= b(i);
end generate;
for i in 0 to 7 loop
a(i) <= b(i);
end loop;Thank you!