VHDL for: generate vs loop

[robmar]

Hello, I'm a beginner at VHDL. I couldn't find an answer to this online:
What is the difference between using the for generate and for loop when performing signal assignments?

EX:

for i in 0 to 7 generate
   a(i) <= b(i);
end generate;

for i in 0 to 7 loop
   a(i) <= b(i);
end loop;

Thank you!

 

[FvM]

The loop statement has to be used in a process. If it's a combinatorial process and the assignment is executed unconditionally it works like the generate statement, just copying the signal. If it's used under an edge sensitive condition like if rising_edge(clk), the assignment generates registers.

 

[robmar]

Thank you for your prompt response.
The generated registers you mentioned in case of an edge condition are generated automatically by the synthesizer, correct?