VHDL file order in ispLever

[davorin]

Does someone know how can I force the file order of VHDL modules for compiling?

 

[jay_ec_engg]

use sequential model in top level file...
use process in the top level file and instantiate models according to ur req.
i hope i understand ur question properly.... as ur super moderator....there will be something in ur question.

 

[lucbra]

I don't know if I understand your question well. Why should your change the compiling order in the first place.
What you can do however, is giving more priority in the mapping & routing, ie setting the constraints (constraints manager). Even after placing, you can manually edit with the EPIC editor.

If you want to keep everything under manual control, you will need to develop your modules in Leonardo or Synplicity, create a JEDEC, and merge then together (again under EPIC).

Regards,

 

[aji_vlsi]

Does someone know how can I force the file order of VHDL modules for compiling?

Not sure what you mean by that - do you mean:

How to compile my packages first and then the entity, tb etc.?

If so, your compiler should provide a way to give a file-list, order your files in a text file and specify that as input to the compiler. Which tool do you use? Also, off-late tools are becoming smarter to figure out "dependencies" themselves, for instance VHDLSimli has a "smart build" option for this. See http://www.symphonyeda.com

Ajeetha
http://www.noveldv.com

 

[raylay]

Does someone know how can I force the file order of VHDL modules for compiling?

what do you meaning ?
you could manual force compiling by your own order.