vhdl file handling......................

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velu.plg

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Code VHDL - [expand]
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library ieee;
    use ieee.std_logic_1164.all;
    use ieee.std_logic_unsigned.all;
    use ieee.std_logic_textio.all;
    use std.textio.all;
 
entity rom_using_file is
GENERIC (N :INTEGER:=260);
    port (
        ce,clk ,clk1,read      :in  std_logic;                     -- Chip Enable
        read_en :in  std_logic;                     -- Read Enable
        address :in integer; -- Address input
        data    :out integer;  -- Data output
        ram1 : inout integer;
        c : inout std_logic
    );
end entity;
architecture behavior of rom_using_file is
 
    -- RAM block 8x256
    type RAM is array (0 to (N-1), 0 to (N-1) )of integer;
    signal mem : RAM ;
    signal inc_row,inc_colom : integer:=0;
    file f1 :text open write_mode is "F:\vlsi project\AV00 _samplecode\imageprocessing\in1.txt";
    -- Subprogram to read a text file into RAM --
    procedure Load_ROM (signal data_word :inout RAM) is
        -- Open File in Read Mode
        file romfile   :text open read_mode is "F:\vlsi project\AV00  _samplecode\imageprocessing\indata.txt";
        
        variable lbuf  :line;
        variable i,j   :integer := 0;
        variable fdata :integer;
    begin
        while not endfile(romfile) loop
            -- read digital data from input file
            readline(romfile, lbuf);
            read(lbuf, fdata);
            data_word(i,j) <= fdata;
            if (clk = '1')then
            i := i+1;
            if (i=(N-1)) then
            j := j+1;
            i:=0;
          end if;
          end if;
          end loop;
           
    end procedure;
 
begin
 
    -- Procedural Call --
    Load_ROM(mem);
    
    process(clk1)
      variable buf : line;
      variable i1 :integer;
      begin
        
        ram1 <= mem(inc_row,inc_colom);
        i1 := ram1;
        
    if (clk1='1')then
      inc_colom <= inc_colom + 1;
      if (inc_colom = 5)then
        inc_row <= inc_row + 1;
      if (read ='1')then
      write (buf ,i1);
      writeline (f1,buf);
    end if;
    end if;
    end if;
    
  end process;



this is my code ...
how to rectify this error ????

** Error: F:/vlsi project/AV00 _samplecode/imageprocessing/rom.vhdl(44): Prefix of indexed name must be an array.
** Error: F:/vlsi project/AV00 _samplecode/imageprocessing/rom.vhdl(290): VHDL Compiler exiting
 
Last edited by a moderator:

You cannot call a procedure outside of a process.

You also need a 'event statement anded with clk = '1' for a proper synchronous process.
 

thanks for ur interest...

same error is occur...

Code VHDL - [expand]
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library ieee;
    use ieee.std_logic_1164.all;
    use ieee.std_logic_unsigned.all;
    use ieee.std_logic_textio.all;
    use std.textio.all;
 
entity rom_using_file is
GENERIC (N :INTEGER:=260);
    port (
        ce,clk ,clk1,read      :in  std_logic;                     -- Chip Enable
        read_en :in  std_logic;                     -- Read Enable
        address :in integer; -- Address input
        data    :out integer;  -- Data output
        ram1 : inout integer;
        c : inout std_logic
    );
end entity;
architecture behavior of rom_using_file is
 
    -- RAM block 8x256
    type RAM is array (0 to (N-1), 0 to (N-1) )of integer;
    signal mem : RAM ;
    signal inc_row,inc_colom : integer:=0;
    file f1 :text open write_mode is "F:\vlsi project\AV00 _samplecode\imageprocessing\in1.txt";
    -- Subprogram to read a text file into RAM --
    procedure Load_ROM (signal data_word :inout RAM) is
        -- Open File in Read Mode
        file romfile   :text open read_mode is "F:\vlsi project\AV00  _samplecode\imageprocessing\indata.txt";
        
        variable lbuf  :line;
        variable i,j   :integer := 0;
        variable fdata :integer;
    begin
        while not endfile(romfile) loop
            -- read digital data from input file 
            readline(romfile, lbuf);
            read(lbuf, fdata);     ------------ [error line:44th] 
            data_word(i,j) <= fdata;
            if (clk'event and clk  = '1')then
            i := i+1;
            if (i=(N-1)) then
            j := j+1;
            i:=0;
          end if;
          end if;
          end loop;
           
    end procedure;
 
begin
 
    -- Procedural Call --
    Load_ROM(mem);
    
    process(clk1)
      variable buf : line;
      variable i1 :integer;
      begin
        
        ram1 <= mem(inc_row,inc_colom);
        i1 := ram1;
        
    if (clk1='1')then
      inc_colom <= inc_colom + 1;
      if (inc_colom = 5)then
        inc_row <= inc_row + 1;
      if (read ='1')then
      write (buf ,i1);
      writeline (f1,buf);
    end if;
    end if;
    end if;
    
  end process;

error:

** Error: F:/vlsi project/AV00 _samplecode/imageprocessing/rom.vhdl(44): Prefix of indexed name must be an array.
** Error: F:/vlsi project/AV00 _samplecode/imageprocessing/rom.vhdl(289): VHDL Compiler exiting

how can i solve it ????
 
Last edited by a moderator:

In addition to what TrickyDicky said, you cannot call a procedure outside a process.
 

velu.plg said:
how to rectify this error ????

** Error: F:/vlsi project/AV00 _samplecode/imageprocessing/rom.vhdl(44): Prefix of indexed name must be an array.
** Error: F:/vlsi project/AV00 _samplecode/imageprocessing/rom.vhdl(290): VHDL Compiler exiting
Click to expand...
1. Are you sure that line 44 that is being flagged is line 44 in your posted code? In the code that you posted, line 44 is an "end if" statement which would not cause the error that you reported. Re-compile and double check exactly which line of code is being flagged and post it here if you want some help.

Unrelated to your question: In your 'Load_ROM' procedure
- Did you really want those spaces in your file name?
- If you intend to synthesize this code, do you really intend to have a two dimensional array of 32 bit integers? RAM is a one dimensional array, not two. If you're implementing a two dimensional structure, you will need to restructure it as a one dimensional array in order to synthesize to internal RAM. If not, the 2d array will be implemented with flip flops...lots of them.
- The "if (clk = '1')then" needs to be removed. Your procedure outputs a table which is performed statically, there should be no dependency on 'clk'.

Kevin Jennings

- - - Updated - - -

TrickyDicky said:
Ive got a feeling of deja Vu.

You cannot call a procedure outside a process.
Click to expand...

Yes you can....yes you can.

Kevin Jennings
 

thanks for ur interest sir,

error line --- 37

i am a stranger for image processing (vhdl+matlab)

i covert the image into pixel using matlab and this is stored in text file (it contain 20700 integer value).

then i want to read that file into memory and perform sobel edge detection using modelsim software.

so , i need to move the sobel operator in that memory ...

this is correct format ?? or give the idea to me...
 

K-J said:
Yes you can....yes you can.

Kevin Jennings
Click to expand...

Dont know why I had it in my head you could not. :S


Velu: I dont really know what you're asking. Your code discribes a rom - there is no transformation in the code. I have no idea what the image is, or the format. WHat you describe seems to just be an image streamer. You're starting sort of the right lines, but you have many problems just trying to read the data from a file. Have you even started writing the sobel edge detection yet?
 

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