[SOLVED] VHDL- Fatal error happens while using variables !!!

Hi guys,
I have a code which can be written briefly as:
----------------
P1: FOR i IN 0 TO 10 GENERATE
PROCESS (clk, reset)
BEGIN
IF clk'EVENT........

X(0,i) <= Y(2i) + Y(2i+1); ---- e.g, X(0,1) <= Y(0,2) + Y(0,3)

END IF;
END PROCESS;
END GENERATE;
--------------

P2: PROCESS (clk, reset)
VARIABLE j : INTEGER := 1;
VARIABLE i : INTEGER := 0;
BEGIN
IF clk'EVENT...........
X(j,i) <= X(j-1, 2i) + X(j-1, 2i+1); ---- e.g, X(1,1) <= X(0,2) + X(0,3)
...
...
...
-----------------------

Could someone help me why i get famous fatal error " signal x has multiple drivers..... " in ModelSim please??????

When i change i & j to any integer number, in process P2, there is no error at all. I mean if i write the code such "X(1,1) <= X(0,2) + X(0,3)", the error will not occur!!!

You didnt show what X is. But I guess its an array of integers or something. You cannot drive an unresolved type from two separate processes. Even if it was a resolved type (like std_logic or std_logic_vector) the result is going to be XXXXX.

So, moral of the story - only assign X in a single process.

Modelsim doens't seem to pick up when x shouldn't assign a default x(0) <= x(0) whenever n is a variable that cannot be equal to 0. Thus, even though the same bits are not (and cannot be) assigned by both processes, the tools will not realize this when the indices are not declared as constants.

you can get away with this by defining X_0, and X_others, and setting X to be some concatenation of the two. This will make it clear to the tools that the processes don't actually assign to the same locations.

Thank you friends,

It seems 2-D arrays are condemned to be assigned only in one process.