VHDL errors in my code?

ERROR:HDLCompiler:806 - "C:\Users\Owner\Documents\vhdl\encoder\priorityencoder.vhd" Line 47: Syntax error near "process".
ERROR:HDLCompiler:841 - "C:\Users\Owner\Documents\vhdl\encoder\priorityencoder.vhd" Line 48: Expecting type void for <behavioral>.

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Code VHDL - [expand]
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
entity priorityencoder is
    port(en_l: in std_logic;                            --Active low enable
          din: in std_logic_vector(3 downto 0); --Active high data input
          dv_l: out std_logic;                          --Valid output active low
          dout: out std_logic_vector(1 downto 0)  --Active high data output
          );
          
end priorityencoder;
 
architecture Behavioral of priorityencoder is
signal en: std_logic;
signal dv: std_logic;
 
begin
en <= not en_l;     --Activation level conversion
dv_l <= not dv;     --Activation level conversion
 
process(din, en)
begin
    if(en = '1' and dv = '1') then
        if(din(0) = '1') then
            dout <= "11";           --LSB has priority
        if(din(1) = '1') then
            dout <= "10";
        if(din(2) = '1') then
            dout <= "01";
        if(din(3) = '1') then   --MSB has least priority
            dout <= "00";
        end if;
    elsif(en = '0') then
        dv <= '0';
        dout <= "00";       
    end if; 
end process;
end Behavioral;

Jorge Jesse Cantu said:

Hi guys! I just coded a 4 to 2 priority encoder and am getting the following errors:



How do I fix these? Here is my code:

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Code VHDL - [expand]
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
entity priorityencoder is
    port(en_l: in std_logic;                            --Active low enable
          din: in std_logic_vector(3 downto 0); --Active high data input
          dv_l: out std_logic;                          --Valid output active low
          dout: out std_logic_vector(1 downto 0)  --Active high data output
          );
          
end priorityencoder;
 
architecture Behavioral of priorityencoder is
signal en: std_logic;
signal dv: std_logic;
 
begin
en <= not en_l;     --Activation level conversion
dv_l <= not dv;     --Activation level conversion
 
process(din, en)
begin
    if(en = '1' and dv = '1') then
        if(din(0) = '1') then
            dout <= "11";           --LSB has priority
        if(din(1) = '1') then
            dout <= "10";
        if(din(2) = '1') then
            dout <= "01";
        if(din(3) = '1') then   --MSB has least priority
            dout <= "00";
        end if;
    else
        en <= '0';
        dv <= '0';
        dout <= "00";
    end if; 
end process;
end Behavioral;

---

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Code VHDL - [expand]
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if  <comparison> then
elsif <comparison> then
elsif <comparison> then
end if;