vhdl error when using component

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity BUTTONDEBOUNCE is
	port( clk 					:in STD_logic;
			btn 					:in STD_logic_vector (3 downto 0);
			button_debounced 	:out STD_logic_vector (3 downto 0));
end BUTTONDEBOUNCE;

architecture Behavioral of BUTTONDEBOUNCE is
	component delay is
		port(
			clk1 			: in STD_logic;
			signal i1	: in integer);
	end component;
	signal i : integer := 500000;
	signal b : STD_logic_vector (3 downto 0) := "0000";
	signal j : integer := 0;
begin
 
	process(btn)
	begin
		for j in 0 to 4 loop
			button_debounced <= b;
			if (btn(i) = '1') then 
				delay1: delay port map (clk, i);
				if (btn(i)='1')
				
					then b(i) <='1'; 
					
					while (btn(i) = '1') loop 
						delay2: delay port map (clk, i); 
					end loop;
					b(i)<='0';
				end if;
			end if;
		end loop;
	end process;

end Behavioral;

entity delay is
	port(	clk1 			: in STD_logic;
			signal i1	: in integer);
end delay;


architecture Behavioral of delay is
signal count 			 : integer :=1;
begin

process(clk1)
begin
	if(rising_edge(clk1)) then
		count <=count+1;
		if(count >= i1) then
			count <=1;
		end if;
	end if;
end process;

end Behavioral;