VHDL down counter using subtractors

[VHDL92]

Hi guys i'm new to this so bear with me.

I've been assigned to program a VHDL code for a 4bit down counter using half/full subtractors. I've got the sample testbench from my supervisor as shown below.

Counter testbench:

library ieee;
use ieee.std_logic_1164.all;

entity mycounter_testbench4 is
end mycounter_testbench4;

architecture mycounter_tb4 of mycounter_testbench4 is

signal count: std_logic_vector(3 downto 0);
signal clk: std_logic:='0';
signal reset: std_logic;

component counter4
port(countut std_logic_vector(3 downto 0);
clk:in std_logic;
reset:in std_logic);

end component;

begin
counter_circuit : counter4
port map(count => count, clk => clk, reset => reset);

clockrocess
begin
wait for 10ns;
clk <= not clk;
end process clock;

test_resetrocess
begin
wait for 5ns; reset <= '1';
wait for 4ns; reset <= '0';
wait;
end process test_reset;

end mycounter_tb4;

Now i'll need to program a code for this and i have some problems. Below are my codes.

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity counter4 is
port(countut std_logic_vector(3 downto 0);
clk:in std_logic;
reset:in std_logic);
end counter4;

architecture behav_counter4 of counter4 is

component ha port (a: in std_logic;
b: in std_logic;
sum: out std_logic;
c_out: out std_logic);
end component;

component fa port (a, b, cin : in std_logic;
sum, c_out : out std_logic);
end component;

signal ain,s,c:std_logic_vector(3 downto 0) :="0000";
signal bin:std_logic_vector(3 downto 0):="0001";

begin
u1:ha port map(a => ain(0), b => bin(0), sum => s(0), c_out => c(0));
u2:fa port map(a => ain(1), b => bin(1), sum => s(1), cin => c(0), c_out => c(1));
u3:fa port map(a => ain(2), b => bin(2), sum => s(2), cin => c(1), c_out => c(2));
u4:fa port map(a => ain(3), b => bin(3), sum => s(3), cin => c(2), c_out => c(3));


counterrocess(clk, reset) --process(sensitivity list)
begin
if reset'event and (reset = '1') then
s <= (others => '0');

elsif clk'event and (clk='1') then
ain <= c xor ain;
s <= ain xor bin;
c <= s and c;


end if;
end process;

count <= s;

end behav_counter4;


Really hope you guys can help me with this. I've got 8 weeks left to submission.

 

[treqer]

and why so hard?

if the task is to make high-speed counter, it's not the fact that the best way.

if clk'event and (clk='1') then
cnter <= cnter +(-) 1;
end if;

 

[VHDL92]

and why so hard?

if the task is to make high-speed counter, it's not the fact that the best way.

if clk'event and (clk='1') then
cnter <= cnter +(-) 1;
end if;

the code i showed above can be compiled.but i could not get the waveform. so i need help on this.

 

[TrickyDicky]

But Treqer also said you dont need to have the code you have got.

you can replace it all with his code.

 

[VHDL92]

But Treqer also said you dont need to have the code you have got.

you can replace it all with his code.

thats the problem. i can't use the quote given because i'm told to use half/full subtactors. so i can't put in any (+) or (-) sign in my codes.