VHDL : delay and synthesis problem....PLEASE HELP !!!

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nikhilsigma

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this is my code....

Code VHDL - [expand]
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity server is
    Port ( a : in  STD_LOGIC;   -- a is the rquests from the user
           b : in  STD_LOGIC;
           ar,ag,al  : out  STD_LOGIC:='0');  -- c is showinh the processing of disk according to request(a)...
end server;
 
architecture Behavioral of server is
signal a1 :integer:=0;
signal a2 :std_logic := '0';
begin
 
    reqA : process (a,a2,a1)   
    begin
        if(a' event and a='1')
            then a1<=a1+1;
        end if;
        if(a2' event and a2='1')              
            then a1<=a1-1;
        end if;
        if(a1>0)
            then
            al<='1';
            ag<='0';
            else
            al<='0';
            if(a2='1')
                then
                ag<='0';
                else
                ag<='1';
            end if;
        end if;
    end process reqA;
    
    
    logic : process 
    begin
        if(a1>0)
            then 
            ar<='1';
            a2<='1';
            wait for 2 sec;   -- wait for 2second clock    
            ar<='0';
            a2<='0';
 
            elsif (a1=0)
            then
            a2<='0';
                        wait until rising_edge(b);  -- wait for small clock
        end if;
    end process logic;
    
 
 
end Behavioral;



so i have 2 problems.....
1. I want to add a delay of 2seconds at the place as shown in syntax....i think it can be done with a counter with a for loop....if yes...please give syntax....
2. tool is showing that "Signal a1 cannot be synthesized, bad synchronous description." so how can i remove this error....

Note : consider signal b as clock....

please help..... :sad:
 

As barry said, don't use wait. That's meant for simulation, not synthesis. In hardware you need, well, hardware to do that delay for you.
 
If you still get "Signal a1 cannot be synthesized, bad synchronous description" as in your first post, then you should fix the bad synchronous coding habit. Did you remove that wait statement yet?
 
i had made that wait until rising_edge(clk).... so now both the wait statements are of this kind only.....

and i am writing vhdl for the first time...
so it would be very helpful, if you could please tell me...what are the bad points in that code....and why ??

Thanks...
 

STOP USING WAIT!

Use:

if rising_edge(clk) then...

It's still not clear what you are trying to do. It LOOKS like you want to generate a 2 sec wide pulse for ar and a2, is that correct? And then you are using the edge of a2 to clock another process?

Maybe you should back up and state exactly what you are TRYING to do rather than hoping we can figure out what your intent is.
 
you have two 'event statements for the same FF. the resources in the FPGA fabric do not support this.
 
First of all thanks to you guys for replying...

My problem statement is.....

Function: A storage server receives requests for accesses to data from one of 4 disks. The server
maintains a different request queue for every disk, and when it receives a request, it adds it to the
queue for the respective disk. Assume that each access keeps the disk busy for 2 seconds, and only
one of the disks can transfer data at a time. If requests to multiple disks are pending, it should use
some strategy to resolve the situation. All requests must be serviced.
Inputs: 4 switches, indicating whether access is requested to the respective disk. Switch is HIGH
means there is a request for a new access. To initiate a new access, turn the switch OFF and then
turn it ON after some time.
Outputs: 4 sets of 3 LED lights each, representing the status of 4 disks. GREEN means ready to accept
new request. RED means data transfer is in progress. ORANGE/YELLOW means requests are queued
for the disk.

so i have to model this server.....
what i am trying to do is.....
Lets says we have 4 disks A,B,C,D

so i thought of making program for one hardisk first.....

process "count" is intended for queing requests coming on a(from external switch), and a1 is the main counter.....a2 is a signal, which is counting the number of requests processed....

and if this works for single disk.....
then i will make 4 processes for aligning and taking request for each disk(process "align" and "count") and one process for processing the requests......which will be sequential (process "main").....triggered by a 2s clock(tempclk).....
process "dispA" is turning the yellow/orange and green leds on and off....



i found out that my last code was not synchronized.....
so now i have written a synchronous code.....here every process starts at every rising edge of clk only........and also i have removed all waits...
but still i am getting some warning while synthesizing the code...


Code VHDL - [expand]
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity server is
    Port ( clk : in  STD_LOGIC;
           ain : in  STD_LOGIC;
           ar: out  STD_LOGIC;
           ao : out  STD_LOGIC;
--          dclk, p,q,r,s : out std_logic;
              ag : out  STD_LOGIC);
end server;
 
architecture Behavioral of server is
signal a,ai,ar1,tempclk : std_logic:='0';
signal a1, a2 : integer :=0;
begin
 
    align :process(clk)   -- aligns the asynchronous input signal to clk.....where a1 is the input from the switch...
    begin
    if(clk='1')
        then
        if(ain='1')
            then
            a<='1';      -- reproduced signal
            else
            a<='0';
        end if;
        ai<=a;        -- reproduced signal delayed by a clock cycle...
    end if;
    end process align;
    
    
    
    count : process(clk)     --  count and record the input requests in a1.
    begin
    if(clk='1')
        then
        if(a='1' and ai='0')
            then
            a1<=a1+1;
--      elsif rising_edge(a2)
--          then
--          a1<=a1-1;
        end if; 
    end if;
    end process count;
    
    
    main:process(tempclk)    -- main process giving delay(processing) on request(a1),
    begin
    if(tempclk='1')
        then
        if(a1-a2>0)         -- difference of a1 and a2 will give the number of pending requests...
            then
            a2<=a2+1;    --a2 keeps the record that how many requests have been processed..
            ar<='1';
            ar1<='1';
            else
            ar<='0';
            ar1<='0';
        end if;
    end if;
    end process main;
            
    
    
    
    
    dispA: process(clk)    -- displaying output on orange/yellow and green leds i.e. signal ao and ag respectively
    begin
    if(clk='1')
        then
        if(a1-a2>0)
            then
            ao<='1';
            ag<='0';
            else
            ao<='0';
            if(ar1='1')
                then
                ag<='0';
                else
                ag<='1';
            end if;
        end if;
    end if;
    end process dispA;
    
 
    delclk : process(clk)  -- generating a clock of 2seconds....in tempclk
    variable i: integer:=0;
    begin
    if(clk='1')
        then
        i:=i+1;
        if(i>5)
            then
            tempclk<=not tempclk;
            i:=0;
        end if;
    end if;
    end process delclk;
 
 
 
end Behavioral;



here are the warning i am getting......

WARNING:Xst:819 - "C:/Xilinx92i/Programs/sync_assign1/sync.vhd" line 44: The following signals are missing in the process sensitivity list:
WARNING:Xst:819 - "C:/Xilinx92i/Programs/sync_assign1/sync.vhd" line 60: The following signals are missing in the process sensitivity list:
WARNING:Xst:819 - "C:/Xilinx92i/Programs/sync_assign1/sync.vhd" line 75: The following signals are missing in the process sensitivity list:
WARNING:Xst:819 - "C:/Xilinx92i/Programs/sync_assign1/sync.vhd" line 95: The following signals are missing in the process sensitivity list:
WARNING:Xst:737 - Found 1-bit latch for signal <ag>.
WARNING:Xst:737 - Found 1-bit latch for signal <ai>.
WARNING:Xst:737 - Found 1-bit latch for signal <ao>.
WARNING:Xst:737 - Found 1-bit latch for signal <ar>.
WARNING:Xst:737 - Found 1-bit latch for signal <tempclk>.
WARNING:Xst:737 - Found 1-bit latch for signal <a>.
WARNING:Xst:737 - Found 32-bit latch for signal <i>.
WARNING:Xst:737 - Found 32-bit latch for signal <a1>.
WARNING:Xst:737 - Found 1-bit latch for signal <ar1>.
WARNING:Xst:737 - Found 32-bit latch for signal <a2>.
WARNING:Xst:2734 - Property "use_dsp48" is not applicable for this technology.
WARNING:Xst:2734 - Property "use_dsp48" is not applicable for this technology.
WARNING:Xst:2734 - Property "use_dsp48" is not applicable for this technology.

please help.....why all these are latches as i have triggered every process by the rising edge of clk...??
 

you have not made synchronous code, you have made level sensitive latches.
First of all: you need to include clk in the process sensitivity list :

process(clk)

secondly - for it to be synchronous you need the following if statement wrapped around your code inside the process:

if rising_edge(clk) then

OR

if clk'event and clk = '1' then

(the first one is prefered).
 
thanks alot for helping.... :grin: :smile:

i have a doubt.....

whats the difference between.....

process(clk)
if rising_edge(clk)
then

and

process(clk)
if clk='1'
then

as in the second case also the process is triggered only by clk transitions and the if statement make sure that only positive edge of clock is accounted.....!! the codes you had given will 110% ensure rising edge.....but i am not able to find the bug in my statement.... :-?


so now i have updated my code.....and most of the warnings were gone.....

Code VHDL - [expand]
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity server is
    Port ( clk : in  STD_LOGIC;
           ain : in  STD_LOGIC;
           ar: out  STD_LOGIC;
           ao : out  STD_LOGIC;
              ag : out  STD_LOGIC);
end server;
 
architecture Behavioral of server is
signal a,ai,ar1,tempclk : std_logic:='0';
signal a1, a2 : integer :=0;
begin
 
    align :process(clk,ain)   -- aligns the asynchronous input signal to clk.....where a1 is the input from the switch...
    begin
    if(rising_edge(clk))
        then
        if(ain='1')
            then
            a<='1';      -- reproduced signal
            else
            a<='0';
        end if;
        ai<=a;        -- reproduced signal delayed by a clock cycle...
    end if;
    end process align;
    
    
    
    count : process(clk,a,ai)     --  count and record the input requests in a1.
    begin
    if(rising_edge(clk))
        then
        if(a='1' and ai='0')
            then
            a1<=a1+1;
        end if; 
    end if;
    end process count;
    
    
    main:process(tempclk,a1,a2)    -- main process giving delay(processing) on request(a1),
    begin
    if(rising_edge(tempclk))
        then
        if(a1-a2>0)         -- difference of a1 and a2 will give the number of pending requests...
            then
            a2<=a2+1;    --a2 keeps the record that how many requests have been processed..
            ar<='1';
            ar1<='1';
            else
            ar<='0';
            ar1<='0';
        end if;
    end if;
    end process main;
            
    
    
    
    
    dispA: process(clk,a1,a2,ar1)    -- displaying output on orange/yellow and green leds i.e. signal ao and ag respectively
    begin
    if(rising_edge(clk))
        then
        if(a1-a2>0)
            then
            ao<='1';
            ag<='0';
            else
            ao<='0';
            if(ar1='1')
                then
                ag<='0';
                else
                ag<='1';
            end if;
        end if;
    end if;
    end process dispA;
    
 
    delclk : process(clk)  -- generating a clock of 2seconds....in tempclk
    variable i: integer:=0;
    begin
    if(rising_edge(clk))
        then
        i:=i+1;
        if(i>5)
            then
            tempclk<=not tempclk;
            i:=0;
        end if;
    end if;
    end process delclk;
 
 
 
end Behavioral;



now the errors which are coming are....


WARNING:Xst:2734 - Property "use_dsp48" is not applicable for this technology.
WARNING:Xst:2734 - Property "use_dsp48" is not applicable for this technology.
 

nikhilsigma said:
WARNING:Xst:2734 - Property "use_dsp48" is not applicable for this technology.
WARNING:Xst:2734 - Property "use_dsp48" is not applicable for this technology.
Click to expand...

What version of ISE are you using? There was a bug before version 10 that would produce this error.
**broken link removed**
If you are using 9.x, Xilinx says you can ignore it.
 
whats the difference between.....

process(clk)
if rising_edge(clk)
then

and

process(clk)
if clk='1'
then
Click to expand...

The big difference is that yes you are correct if you are simulating, but the synthesisor ignores the sensitivity list when it compiles, and looks just at the logic. The sensitity list is only for simulation. So, the synthesisor just sees a level sensitive latch in the second process.

This is not a bug or a problem with VHDL, it is the way it always has been and always will be.
 
The statement: if clk='1' is not a synchronous one, it's only looking at a level. What you want is: if clk='1' and clk'event. THAT is the same as 'if rising_edge...
 
barry said:
The statement: if clk='1' is not a synchronous one, it's only looking at a level. What you want is: if clk='1' and clk'event. THAT is the same as 'if rising_edge...
Click to expand...

But in simulation, using:

process(clk)
begin
if clk = '1' then

will look as though you have synchronous code. The process is only sensitve to a clk'event, and will only change signals when clk='1', hence looking like a synchronous process.
 

So while synthesizing in VHDL, is SENSITIVITY LIST useless.....i mean to say that are following two codes same for synthesizer.....

process(clk)
if rising_edge(clk)
then

and

process
if rising_edge(clk)
then

i.e. it doesn't matter what sensitivity list we make.....and if it matter then please correct me and tell how....
 

it does matter. The 2nd example is illegal VHDL because a process must have either a sensitivity list OR contain a wait statement.
The sensitivity list is essential for simulation, because without a sensitivity list, the process does nothing and will never do anything, except for the first runthrough at sim start.

A sensitivity list tells the simulator which signals should trigger the process. In the case of the top one, the process gets "run" whenever there is a 'event on the clk signal.
 



ok i got that it is needed for simulation and most of the textbooks(based on simulation) also tells samething.....but i was asking about synthesizer as u had said that it doesn't give any importance to sensitivity list....??



also my second question is, Why all the books teaches VHDL from the point of view of Simulations using wait etc, although in reality we can't synthesize those... :-(
and please tell me some book or something which teaches synthesizable VHDL.
 

wait is generally used in testbenches where you want to generate verifying pattern.
 

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