dohzer
Member level 1
- Joined
- Oct 25, 2008
- Messages
- 39
- Helped
- 0
- Reputation
- 0
- Reaction score
- 0
- Trophy points
- 1,286
- Activity points
- 1,636
vhdl concatenate std_logic_vector
I've got two (probably simple) VHDL questions.
Firstly, I've got a std_logic_vector signal I want to concatenate with a certain number of zeros to pad it out.
What would I put where the ??? is to take "small_signal" padded with zeros in the upper four bits and assign it to "large_signal"?
I could write...
... but if I change the width of each signal, I'd have to change the number of zeros accordingly.
I'm assuming the solution I'm after would involve some sort of "(LARGE_WIDTH downto LARGE_WIDTH)" statement, combined with "others => '0'", but I really don't know the syntax to use.
My second question is to do with converting an integer to a single bit.
Is there a simple way to use a single bit from an integer type variable's binary representation and assign it to a signal?
Is there a single line assignment I can use to assign the bits of "count" to their respective signals, or do I need to use another temporary vector to convert count to std_logic and then split the bits out from that?
PS. Sorry if this is the wrong forum... I noticed it is for "device specific VHDL/Verilog/SystemC questions" but wasn't sure where non-specific HDL questions should go.
I've got two (probably simple) VHDL questions.
Firstly, I've got a std_logic_vector signal I want to concatenate with a certain number of zeros to pad it out.
Code:
constant SMALL_WIDTH : integer := 4;
constant LARGE_WIDTH : integer := 8;
...
signal small_signal : std_logic_vector(SMALL_WIDTH-1 downto 0);
signal large_signal : std_logic_vector(LARGE_WIDTH-1 downto 0);
...
large_signal <= ???What would I put where the ??? is to take "small_signal" padded with zeros in the upper four bits and assign it to "large_signal"?
I could write...
Code:
large_signal <= "0000" & small_signal;I'm assuming the solution I'm after would involve some sort of "(LARGE_WIDTH downto LARGE_WIDTH)" statement, combined with "others => '0'", but I really don't know the syntax to use.
My second question is to do with converting an integer to a single bit.
Is there a simple way to use a single bit from an integer type variable's binary representation and assign it to a signal?
Code:
signal sig1,sig2,sig3,sig4 : std_logic;
...
for count in 0 to 16 loop
sig1 <= <bit_0_of_count>;
sig2 <= <bit_1_of_count>;
sig3 <= <bit_2_of_count>;
sig4 <= <bit_3_of_count>;
...
end loop;Is there a single line assignment I can use to assign the bits of "count" to their respective signals, or do I need to use another temporary vector to convert count to std_logic and then split the bits out from that?
PS. Sorry if this is the wrong forum... I noticed it is for "device specific VHDL/Verilog/SystemC questions" but wasn't sure where non-specific HDL questions should go.