VHDL Code giving Exceptional error

Here is the code for decoder taken from "Circuit Design with VHDL" by Volnei A Pedroni.
This code works well if Input port is given 10 bits i.e(9 downto 0) and Output1 at(1023 downto 0),.. making it a 10x1024 decoder,...
This code also works fine with Input (12 downto 0) and output1 at(8191 downto 0)... making it a 12x8192 decoder
but when I increase input bits further to (15 downto 0) then it doesnt synthesize and gives "An Exceptional Error message".
I wanted to know what is the problem..........


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity decoder is
port (input : in std_logic_vector (13 downto 0);

output1: out std_logic_vector (16383 downto 0));
end decoder;

architecture Behavioral of decoder is

begin
process (input)
variable temp1 : STD_LOGIC_VECTOR (output1'HIGH DOWNTO 0);
Variable temp2 : Integer Range 0 to output1'HIGH;
begin
temp1 :=(others =>'1');
temp2 :=0;
for i in input'RANGE LOOP
if (input(i)='1') then
temp2:=2*temp2+1;
else
temp2:= 2*temp2;
end if;
end loop;
temp1(temp2):='0';
output1<=not temp1;
end process;
end Behavioral;

Your synthesis tool is probably not supporting devices with 65536 outpin pins? :smile:

Typically if you have an insane number of io pins in the TOP level of your design, that would mean an insane number of pins on the actual physical hardware. And as of yet we still don't have any 324876238476 pin fpga's. So as FvM points out, it because the synth tool doesn't support that many io's on a device.

And while you may not intend to put this design in an actual device, the synth tool couldn't care less about your intentions. It could try, but it would require a serious amount of cpu cycles. You'd need at least a quad core for that.