vipinlal
Full Member level 6
I want the signals to change as shown in the following timing diagram.The inputs are "busy" and "clk" and output is "dataenable".
These signals are used for interfacing my module with another module.Can anyone give a VHDL code or hardware circuit for this.Just plain ideas are also welcome.
The test bench used for creating this wave form is given below:
DataEnable <= '1';
wait for clk_period*2 ns;
DataEnable <= '0';
wait until Busy = '0';
thanks in advance,
vipin
These signals are used for interfacing my module with another module.Can anyone give a VHDL code or hardware circuit for this.Just plain ideas are also welcome.
The test bench used for creating this wave form is given below:
DataEnable <= '1';
wait for clk_period*2 ns;
DataEnable <= '0';
wait until Busy = '0';
thanks in advance,
vipin