Hi
Just a few points. First, you started 3 threads and hijacked a fourth to discuss your problem. This is considered bad form and makes people not want to help you. Keep that in mind for the future.
Secondly, in spite of what I just said, people here have already helped you. Alot. You have kindly been given VHDL code that will generate the waveforms in figure 2 and 3 of the SI4136 datasheet. Did you study this code? If you put 18-bit data and a 4-bit address on the ports of the VHDL module, then set its GO port to high, it will send the serial data out of the FPGA.
You were also given a testbench, and a script that shows you the values that someone wrote to the synthesizer to configure it.
And you were given a testbench to simulate it.
All you have to do if you want to implement this in an FPGA is write a VHDL module that will, upon power up or some other command. Repeatedly put valid data and address on the ports of the synthesizer module, assert go, and wait for sent to go high before sending more data.
Mote than half of your work has been done by other people, so since this is your project, you should do the rest. Sure, you may not know how to do it at the moment, so do some research and you will be better for it.
r.b.