vhdl code for multiplicative inverse modulo 2^4+1

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manasa4

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hello,can any one explain how to get multiplicative inverse for 4 bit input,i.e,for modulo 17(2^4+1),i have written a code but its not being run ,
number in integer multiplicative inverse\
0 0
1 1
2 9
3 6
4 13
5 7
6 3
7 5
8 15
9 2
10 12
11 14
12 10
13 4
14 11
15 8 


Code VHDL - [expand]
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
entity mulinv is
port(x:in std_logic_vector(3 downto 0);
      z:out std_logic_vector(3 downto 0));
end mulinv;
 
architecture Behavioral of mulinv is
signal xi,zi,t1,t2,y,q:integer;                              
begin
process(x)
begin
xi<=conv_integer(x);
t2<=1;
 if (xi=1) then zi<=1;
 elsif (xi=0) then zi<=0;
 else
   t1<=17/xi;
   y<=17 mod xi;
   if(y=1) then zi<=(1-t1);
    else
        while (y/=1) loop
             q<=xi/y;
            xi<=xi mod y;
             t2<=t2+(q*t1);
             if xi=1 then zi<=t2;
             else  q<=y/xi;
                   y<=y mod xi;
                     t1<=t1+(q*t2);
 
              end if;
             end loop; 
 
         end if;
  zi<=(1-t1);
 end if ;
 
z<=conv_std_logic_vector(zi,4);
end process;    
  
end Behavioral;
 
Last edited by a moderator:

but its not being run
Click to expand...
What do you mean? the code isn't synthesizable, because the iteration count can't be determined by the synthesis tool?
 

at 4b, the best choice will be a lookup table. you can declare that as a constant in VHDL for this size.
Code: 
 type int_array is array (natural range <>) of integer;
constant MULT_INV : int_array(0 to 15) := (0,1,9,6,13,7,3,5,15,2,12,14,10,4,11,8 );
signal x : integer range 0 to 15;
signal y : integer range 0 to 15;
...

y <= MULT_INV(x);

assuming the numbers you provided were correct.
 

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