vhdl code for frquency divider by 2,3,4,12

[vive-sri]

hi,
for my project i ve to get 4 different frequencies(10kHZ,20kHZ,30kHZ,40kHZ) from one clock. So I thought to take common frequency as 120 and going to divide by 12 , 6, 4, 3 inorder to get 10,20,30,40 kHz.. is it ok? i dont ve any idea. i hope u l help me.

 

[VishwanathAmbli]

this is the code for freq/3 , you can implement /2,/4 by just using flipflops or counters.... divide by even number is easy... implement a counter a jst output from one pin of the counter and you have ur freq/2 /4 etc...

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this is the code for freq/3 , you can implement /2,/4 by just using flipflops or counters.... divide by even number is easy... implement a counter a jst output from one pin of the counter and you have ur freq/2 /4 etc...

 

[vive-sri]

thank you for ur code. i need to implement synchronous frequencies from one clock. can i divide by 3,4,6,12 in same coding?

 

[K-J]

Your code, while getting the idea across has a couple of problems:
- Counter is of type std_logic_vector but you're doing math with it (adding 1). This implies that you're using non-standard package std_logic_arith but you didn't include the statement to use std_logic_arith in your code. Counter should be of type unsigned and the ieee.numeric_std package should be used instead. In any case, without using the appropriate package, the code 'as-is' will not compile.
- Counter should not really be 'inout' but should be 'buffer'. There is no circumstance where some external entity will be able to input a value on 'counter' which is what is implied by 'inout'. Mode 'buffer' says that the signal is an output but is also referenced in the code (i.e. counter <= counter + 1);
- There really is no reason why counter should be on the entity, it is simply a signal that is used internally. It would also have been better to simply define counter as being an integer in the range 0 to numb-1.
- Although you have a generic 'numb' for specifying the max count, your code will only work with 'numb=3' because of your initialization of 'counter' in the entity as well as the assignment of "counter<="000";" in the code
- The width of counter isn't correct. It is declared to be 'numb-1 downto 0' which implies, since you're using it as a number' that it can count to 7, but the max is 3. The number of bits in 'counter' is actually the ceil(log2(numb)). But also see the previous comment that counter should really be declared as an integer.

But overall your example is a good one for showing reusable code. Although you can say that dividing by 2 or 4 is easy and don't need to use this entity, there is no reason to not use the entity. In the OP's case, he would instantiate four of your entities and use generic of 3, 4, 6 and 12 and let the synthesizer optimize as necessary.

Kevin Jennings