VHDL code for dividing integers

[WR]

Hi,
Can anyone send a VHDL code for dividing integers in VHDL.

Thanks.

 

[sriram317]

library ieee;
use ieee.std_logic_1164.all;

entity division is
port ( a : in integer range 0 to 255;
b : in integer range 0 to 17;
quo : out integer range 0 to 17);
end division;

architecture structure of division is

begin
process(a,b)
variable var : integer range 0 to 255;
variable count,i : integer range 0 to 127;

begin
i:=0; var:=a;count:=0;
for i in 127 downto 0 loop
if (var>=b) then var :=var-b;count:=count+1;
else
quo<=count;exit;
end if;
end loop;
end process;
end structure;

 

[TrickyDicky]

Mine works better:

Code:

entity division is
port ( a : in integer range 0 to 255;
b : in integer range 0 to 17;
quo : out integer range 0 to 17);
end division;

architecture structure of division is

begin

process(a,b)
begin
  quo <= a / b;
end process;

 

[sriram317]

mine works better:

Code:

entity division is
port ( a : In integer range 0 to 255;
b : In integer range 0 to 17;
quo : Out integer range 0 to 17);
end division;

architecture structure of division is

begin

process(a,b)
begin
  quo <= a / b;
end process;

yours wont synthesize in xilix !!

 

[TrickyDicky]

that was never the question.

 

[vipinlal]

Here is a synthesisable code for unsigned number division. You can use this code, just convert the integer number before passing it to the function.
VHDL coding tips and tricks: A VHDL function for division two unsigned numbers